Semiconductor handler for rapid testing

• US 6,717,115 B1
• Filed: 06/01/2000
• Issued: 04/06/2004
• Est. Priority Date: 04/25/2000
• Status: Expired due to Term

• Current Assignee: Teradyne Incorporated
• Original Assignee: Teradyne Incorporated
• Inventors: Moore, John D., Pfahnl, Andreas C.
• Primary Examiner(s): PAIK, SANG YEOP
• Application Number:
  US09/585,453
• Time in Patent Office: 1,405 Days
• Field of Search: 219/444.1, 219/544, 118/724, 118/725, 118/728, 118/729, 165/80.2, 165/80.3, 165/80.4, 165/80.5
• US Class Current: 219/444.1
• CPC Class Codes: H01L 21/67103 mainly by conduction
• CPC Class Codes: H01L 21/67109 mainly by convection

Abstract

A strip, leadframe or panel type handling device for use in testing semiconductor components. The handling device has a thermal plate assembly with embedded electrical resistance heaters. The heaters are separately controlled in zones to provide uniform temperature across the plate for elevated temperature testing. Cooling channels are formed in the plate. Intermingling channels are provided to allow different types of cooling fluids to be used to cool at different rates or hold a cold temperature at different levels. The cooling channels can likewise be provided in zones to promote temperature uniformity. Vacuum channels are used to hold the semiconductor parts under test in close contact with the thermal plate.

Claims

1. A semiconductor handling system having a thermal plate comprising:

a) a first member having a plurality of holes therethrough;

b) a second member adjacent the first member having vacuum channels formed therethrough, the vacuum channels connected to the holes;

c) an electrical resistance heater embedded in the thermal plate; and

d) a fluid passage, having fluid inlet and a fluid outlet, formed by a channel in a surface of at least one of the first member or the second member.

2. The semiconductor handling system of claim 1 adapted to control the temperature of a plurality of semiconductor devices in a strip, wherein the plurality of holes are aligned with the semiconductor devices in the strip.

3. The semiconductor handling system of claim 1 additionally comprising a source of cooling fluid switchably coupled to the fluid inlet of the channel.

4. The semiconductor handler of claim 3 wherein the source of cooling fluid provides a cooling fluid that provides multi-phase flow in the channel.

5. The semiconductor handling system of claim 1 additionally comprising a plurality of protrusions extending into the channel.

6. The semiconductor handler of claim 1 wherein the electrical resistance heater comprises at least three separately controlled resistance heaters.

7. The semiconductor handler of claim 6 wherein the thermal plate is rectangular having a longer axis with a first end and a second end at opposing ends of the longer axis and an intermediate section between the ends, and wherein a resistance heater is disposed near each of the first end and the second end and in the intermediate section.

8. A semiconductor handling system comprising

a) a thermal plate comprising:

i) an upper surface having a plurality of holes therein;

ii) an interior region having;

A) vacuum channels formed therein, the vacuum channels connected to the holes;

B) an electrical resistance heater embedded in the interior region; and

C) a channel, having fluid inlet and a fluid outlet, embedded in the interior region;

b) a source of cooling fluid coupled to the channel through a flow control device; and

c) a control system operatively connected to the electrical resistance heater and the flow control device to control the temperature of the upper surface by regulating power to the resistance heater and actuating the flow control device.

9. The semiconductor handling system of claim 8 wherein the source of cooling fluid is liquid nitrogen.

10. The semiconductor handling system of claim 8 wherein the source of cooling fluid is air.

11. The semiconductor handling system of claim 8 additionally comprising a second channel having a fluid inlet and a fluid outlet embedded in the interior region.

12. The semiconductor handling system of claim 11 additionally comprising a source of cooling fluid coupled to the channel and a second source of cooling fluid coupled to the second channel.

13. The semiconductor handling system of claim 12 wherein the source of cooling fluid provides a closed loop refrigerant.

14. The semiconductor handling system of claim 13 wherein the second source of cooling fluid provides a fluid that is a cryogenic fluid.

15. The semiconductor handling system of claim 12 additionally comprising:

a) a flow control valve coupled between the source of cooling fluid and the channel;

b) a second flow control valve coupled between the second source of cooling fluid and the second channel;

c) a controller coupled to the first flow control valve and the second flow control valve that operates to open the second flow control valve to lower the temperature of the thermal plate to a temperature required for low temperature operation.

16. The semiconductor handling system of claim 15 wherein the second source of cooling fluid provides liquid nitrogen.

17. The semiconductor handling system of claim 16 wherein the source of cooling fluid provides a closed loop refrigerant.

18. The semiconductor handling system of claim 15 wherein the source of cooling fluid provides compressed air.

19. The semiconductor handler of claim 8 additionally comprising a strip of semiconductor devices disposed on the upper surface, wherein the temperature of the semiconductor devices is controlled by increasing the heat output of the electrical resistance heater when the temperature is below a desired set point.

20. The semiconductor handler of claim 19 wherein the source of cooling fluid provides a cooling fluid that provides multi-phase flow in the channel.

21. The semiconductor handler of claim 19 wherein the source of cooling fluid provides a cooling fluid that includes liquid nitrogen.

22. A semiconductor handling system comprising

a) a thermal plate comprising:

i) an upper surface having a plurality of holes therein;

ii) an interior region having;

A) vacuum channels formed therein, the vacuum channels connected to the holes;

B) an electrical resistance heater embedded in the interior region; and

C) a channel, having fluid inlet and a fluid outlet, embedded in the interior region;

b) an electromechanical component adapted to move semiconductors within the handling system;

c) a switching unit, coupled to the electrical resistance heater and the electromechanical component, adapted to switch power to the electromechanical component to enable movement of the semiconductors within the handling system and the electrical resistance heater and to reduce power to the electrical resistance heater when power is switched to the electromechanical component; and

d) a second electrical resistance heater, whereby heat is generated when the electromechanical device is receiving power, but at a lower level than when the electromechanical device is not receiving power.

23. A semiconductor handling system comprising:

a) a thermal plate comprising;

i) an upper surface having a plurality of holes therein;

ii) an interior region having;

A) vacuum channels formed therein, the vacuum channels connected to the holes;

B) an electrical resistance heater embedded in the interior region; and

C) a channel, having fluid inlet and a fluid outlet, embedded in the interior region;

b) a source of cooling fluid coupled to the channel through a flow control device;

c) a control system operatively connected to the electrical resistance heater and the flow control device; and

d) a second source of cooling fluid coupled to a channel in the plate, the second source of cooling fluid having a lower temperature than said source of cooling fluid.

24. The semiconductor handler of claim 23 wherein the temperature of the plate is decreased to a cold test temperature by increasing the flow of the second source of cooling fluid and is controlled about a test temperature by regulating the flow of said first mentioned cooling fluid.

25. The semiconductor handler of claim 23 wherein the second source of cooling fluid provides a cooling fluid that provides multi-phase flow in the channel.

26. The semiconductor handler of claim 25 wherein the second source of cooling fluid provides a fluid comprising liquid nitrogen.