Semiconductor devices fabricated using sputtered silicon targets

• US 6,717,178 B2
• Filed: 08/13/2002
• Issued: 04/06/2004
• Est. Priority Date: 05/22/2000
• Status: Expired due to Fees

• Current Assignee: Sharp Laboratories of America Incorporated (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Laboratories of America Incorporated (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Nakata, Yukihiko, Voutsas, Apostolos, Hartzell, John
• Primary Examiner(s): LE, DUNG ANH
• Application Number:
  US10/218,744
• Publication Number:
  US 20020192933A1
• Time in Patent Office: 602 Days
• Field of Search: 257/50, 257/52, 257/58, 257/66, 257/67, 257/347, 257/618, 257/77, 257/78, 257/394, 257/462, 438/592, 438/482
• US Class Current: 257/52
• CPC Class Codes: C23C 14/3414 Metallurgical or chemical aspects of target preparation, e.g. casting, powder metallurgy
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02422 Non-crystalline insulating materials, e.g. glass, polymers
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02579 P-type
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/02686 Pulsed laser beam
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate

Abstract

A thin film transistor includes an active silicon layer deposited by physical vapor deposition (PVD), wherein a silicon precursor is doped with impurities prior to use as a target in the PVD chamber, wherein the precursor has a resistivity in the range of about 0.5 Ω-cm<ρ_s<60 Ω-cm; and wherein the target includes plural, rectangular tiles wherein all individual tiles are larger than 8.5 inches square.

Claims

1. In a thin film transistor, an active silicon layer deposited by physical vapor deposition (PVD), wherein a silicon precursor is doped with impurities prior to use as a target in the PVD chamber, and wherein said precursor has a resistivity in the range of about 0.5 Ω

-cm<

ρ

_s<

60 Ω

-cm;

wherein said target includes plural rectangular tiles wherein all individual tiles are larger than 8.5 inches square.

2. The thin film transistor of claim 1 wherein said precursor has a resistivity in the range of about 0.5 Ω

-cm<

ρ

_s<

20 Ω

-cm.

3. The thin film transistor of claim 1 wherein said silicon precursor is p-type silicon.

4. The thin film transistor of claim 1 wherein said silicon precursor is a material taken from the group of materials consisting of single crystal silicon and polysilicon.

5. The thin film transistor of claim 1 wherein said target is a single tile.

6. A liquid crystal display (LCD), including plural thin film transistors (TFTs) therein, wherein each TFT includes an active silicon layer deposited by physical vapor deposition (PVD), wherein a silicon precursor is doped with impurities prior to use as a target in the PVD chamber, and wherein said precursor has a resistivity in the range of about 0.5 Ω

-cm<

ρ

_s<

60 Ω

-cm;

wherein said target includes plural, rectangular tiles wherein all individual tiles are larger than 8.5 inches square.

7. The thin film transistor of claim 6, wherein said precursor has a resistivity in the range of about 0.5 Ω

-cm<

ρ

_s<

20 Ω

-cm.

8. The thin film transistor of claim 6 wherein said silicon precursor is p-type silicon.

9. The thin film transistor of claim 6 wherein said silicon precursor is a material taken from the group of materials consisting of single crystal silicon and polysilicon.

10. The thin film transistor of claim 6 wherein said target is a single tile.