Lateral device with improved conductivity and blocking control

• US 6,717,230 B2
• Filed: 08/27/2002
• Issued: 04/06/2004
• Est. Priority Date: 10/17/2001
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Kocon, Christopher B.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Huynh, Andy
• Application Number:
  US10/228,420
• Publication Number:
  US 20030071320A1
• Time in Patent Office: 588 Days
• Field of Search: 257/328, 257/330, 257/374, 257/487, 257/491, 257/492
• US Class Current: 257/487
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An LDMOS device is made on a semiconductor substrate 112. It has an N+ source and drain regions 120, 132 are formed within a P well region 122. An interlevel dielectric layer 140 encapsulates biased charge control electrodes 142a and they control the electric field within the area of the drift region 14 between P-base 122 and the N drain region 132 to increase the reverse breakdown voltage of the device. This permits the user to more heavily dope the drift region and achieve a lower on resistance.

Claims

1. A lateral transistor device comprising:

a lightly doped layer of semiconductor material having first and second more heavily doped regions of a first conductivity type formed along a surface thereof;

a third region of a second conductivity type between the first and second regions;

a lightly doped region of the first conductivity type between the second and third regions;

a control electrode positioned to enable conduction through the third region; and

a biasing electrode structure positioned along the third region to alter the electric field in the third region.

2. The device of claim 1 wherein the biasing electrode structure is formed in a trench along the third region.

3. The device of claim 1 wherein the biasing electrode structure comprises a plurality of electrodes along the third region.

4. The device of claim 1 wherein the biasing electrode structure comprises a plurality of field control electrodes along the third region, each configured to apply a voltage with respect to a different portion of the third region.

5. The device of claim 4 wherein each field control electrode is capable of applying a different bias voltage with respect to the third region.

6. The device of claim 1 configured as a field effect transistor wherein the first region comprises a source, the second comprises a drain and the third region comprises a channel region.

7. The device of claim 1 wherein the third region comprises a field effect channel region and the lightly doped region of the first conductivity type comprises a drift region.

8. The device of claim 1 wherein the biasing electrode structure comprises multiple electrodes extending into the layer from the surface.

9. The device of claim 1 wherein the biasing electrode structure comprises an electrode extending over the lightly doped region and into the layer on opposing sides of the lightly doped region in a U-shape formation.

10. The device of claim 1 wherein the lightly doped region of the first conductivity type extends into the layer from the surface and the biasing electrode structure comprises one or more electrodes also extending into the layer from the surface.

11. The device of claim 1 wherein the second more heavily doped region is formed in a trench extending from the surface into the layer.

12. The device of claim 1 wherein the biasing electrode structure is electrically isolated from the lightly doped region of the first conductivity type.

13. A lateral transistor device with enhanced breakdown voltage, comprising:

a lightly doped layer of semiconductor material having more heavily doped source and drain regions of a first conductivity type formed therein;

a channel region of a second conductivity type adjacent the source region and between the source and drain regions;

a drift region of the lightly doped semiconductor material disposed between the channel and the drain regions;

a control electrode disposed over the channel region for controlling the flow of current between the source and drain regions; and

bias electrodes disposed adjacent the drift region to alter the electric field in the drift region to increase reverse breakdown voltage.

14. The device of claim 13 wherein the biasing electrodes comprises multiple electrodes extending into the layer from the surface.

15. The device of claim 14 wherein the biasing electrodes comprises pairs of electrodes spaced apart from each other on opposite sides of the drift region.

16. The device of claim 15 wherein each one of the pairs of the biasing electrodes are opposite one another.

17. The device of claim 14 wherein the electrodes are spaced on opposite sides of the drift region and are offset with respect to the electrodes on opposite sides of the drift region.

18. The device of claim 13 wherein the electrodes are enclosed in a dielectric material.

19. The device of claim 18 wherein each bias electrode is enclosed in its own dielectric material.

20. The device of claim 18 wherein bias electrodes on opposite sides of the drift region are enclosed in a common dielectric material.

21. The device of claim 18 wherein pairs of bias electrodes on opposite side of the drift region are enclosed in a common dielectric.

22. The device of claim 13 wherein electrodes enclose the drift region.

23. The device of claim 22 wherein the bias electrodes enclose the drift region of three sides.

24. The device of claim 13 wherein the biasing electrode structure comprises an electrode extending over the lightly doped region and into the layer on opposing sides of the lightly doped region in a U-shape formation.