Chip scale packages performed by wafer level processing

• US 6,717,245 B1
• Filed: 06/02/2000
• Issued: 04/06/2004
• Est. Priority Date: 06/02/2000
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Kinsman, Larry D., Akram, Salman
• Primary Examiner(s): Eckert, George
• Assistant Examiner(s): Chu, Chris C.
• Application Number:
  US09/586,243
• Time in Patent Office: 1,404 Days
• Field of Search: 257/678, 257/788, 257/789, 257/792, 257/793, 257/794, 257/690, 257/787
• US Class Current: 257/678
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/274 by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 2224/29111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/8121 using a reflow oven
• CPC Class Codes: H01L 2224/8122 with energy being in the form of electromagnetic radiation
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 2224/83851 : being an anisotropic conductive adhesive
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/32 : Holders for supporting the complete device in operation, i.e. detachable fixtures H01L23/40 takes precedence
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/28 : Structure, shape, material or disposition of the layer connectors prior to the connecting process
• CPC Class Codes: H01L 24/72 : Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 29/0657 : characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10157 : at the active surface
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/1579 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy

Abstract

Channels are formed that pass through an active surface of a semiconductor substrate to provide isolation between adjacent active surface regions defining individual die locations. Bond pads on the substrate are bumped with intermediate conductive elements, after which a material used to encapsulate the active surface is applied, filling the channels and covering exposed peripheral edges of the active surface integrated circuitry. The encapsulant is then planarized to expose the ends of the bumps. External conductive elements such as solder balls are then formed on the exposed bump ends. The semiconductor wafer is diced in alignment with the channels to singulate the semiconductor devices, the encapsulant in the channels keeping the edges of the integrated circuitry substantially hermetically sealed.

Claims

1. A semiconductor device comprising:

a semiconductor element having an active surface bounded by an inside perimeter of a plurality of channels;

at least one bond pad over the active surface;

an intermediate conductive element associated with the at least one bond pad and projecting from the active surface;

an encapsulant layer over at least the active surface of the semiconductor element and the plurality of channels, the intermediate conductive element having a surface exposed through the encapsulant layer, the exposed surface substantially conforming to a surface of the encapsulant layer;

depressions in the surface of the encapsulant layer over the channels; and

an external conductive element disposed over the intermediate conductive element, the external conductive element contacting the intermediate conductive element at the exposed surface of the intermediate conductive element and projecting beyond the surface of the encapsulant layer.

2. The semiconductor device of claim 1, wherein the encapsulant layer includes at least one of filled polymers, epoxies, silicones, silicone-carbon resins, polyimides, polyurethanes and glasses.

3. The semiconductor device of claim 1, wherein the intermediate conductive element includes at least one of solder, gold, aluminum, conductive epoxy, conductor-filled epoxy and metal-filled elastomer.

4. The semiconductor device of claim 1, wherein the external conductive element includes at least one of solder, conductive epoxy, conductor-filled epoxy, and an anisotropically conductive film.

5. The semiconductor device of claim 1, further including a second encapsulant layer over a back side of the semiconductor element and separate from the encapsulant layer over at least the active surface of the semiconductor element and the plurality of channels.

6. The semiconductor device of claim 1, wherein the semiconductor element comprises a plurality of unsingulated semiconductor dice.

7. The semiconductor device of claim 6, wherein the plurality of unsingulated semiconductor dice are attached as a group to a carrier substrate forming a multi-chip module.

8. The semiconductor device of claim 1, wherein the semiconductor element comprises a singulated semiconductor die having an area defined by a plurality of exposed sides of the semiconductor element around an outside perimeter of the plurality of channels.

9. The semiconductor device of claim 1, further comprising a bond pad between the intermediate conductive element and the external conductive element.

10. The semiconductor device of claim 1, wherein the external conductive element comprises a bond pad extending laterally over the surface of the encapsulant layer.

11. A semiconductor device comprising:

a semiconductor substrate element having an active surface bounded by an inside perimeter of a plurality of channels;

at least one bond pad over the active surface;

an intermediate conductive element associated with the at least one bond pad and extending over the active surface to a peripheral edge of the semiconductor substrate element; and

an encapsulant layer over at least the active surface of the semiconductor substrate element and the plurality of channels, the encapsulant layer leaving exposed an end portion of said intermediate conductive element substantially coplanar with a surface of the encapsulant layer on the peripheral edge of the semiconductor substrate element.

12. The semiconductor device of claim 11, wherein the encapsulant layer includes at least one of filled polymers, epoxies, silicones, silicone-carbon resins, polyimides, and polyurethanes.

13. The semiconductor device of claim 11, wherein the intermediate conductive element includes at least one of solder, gold, aluminum, conductive epoxy, conductor-filled epoxy and metal-filled elastomer.

14. The semiconductor device of claim 11, further including a second encapsulant layer over a back side of the semiconductor substrate element and separate from the encapsulant layer over at least the active surface of the semiconductor substrate element and the plurality of channels.

15. The semiconductor device of claim 11, wherein the semiconductor substrate element comprises a plurality of unsingulated semiconductor dice.

16. The semiconductor device of claim 15, wherein the plurality of unsingulated semiconductor dice are attached as a group to a carrier substrate forming a multi-chip module.

17. The semiconductor device of claim 11, wherein the semiconductor substrate element comprises a singulated semiconductor die having an area defined by a plurality of exposed sides of the semiconductor substrate element around an outside perimeter of the plurality of channels.

18. The semiconductor device of claim 11, wherein the intermediate conductive element comprises a circuit trace.

19. A semiconductor device comprising:

a semiconductor substrate element having an active surface bounded by an inside perimeter of a plurality of channels;

at least one bond pad over the active surface;

an intermediate conductive element associated with the at least one bond pad and projecting from the active surface

an encapsulant layer over at least the active surface of the semiconductor substrate element and the plurality of channels, the encapsulant layer leaving exposed an end portion of the intermediate conductive element substantially coplanar with a surface of said encapsulant layer; and

an external conductive element disposed over the surface of the encapsulant layer, the external conductive element contacting the intermediate conductive element at the exposed end portion of the intermediate conductive element and extending therefrom over and in contact with the surface of the encapsulant layer to a peripheral edge of the semiconductor substrate element.

20. The semiconductor device of claim 19, wherein the encapsulant layer includes at least one of filled polymers, epoxies, silicones, silicone-carbon resins, polyimides, and polyurethanes.

21. The semiconductor device of claim 19, further including a second encapsulant layer over a back side of the semiconductor substrate element and separate from the encapsulant layer over at least the active surface of the semiconductor substrate element and the plurality of channels.

22. The semiconductor device of claim 19, wherein the semiconductor substrate element comprises a plurality of unsingulated semiconductor dice.

23. The semiconductor device of claim 22, wherein the plurality of unsingulated semiconductor dice are attached as a group to a carrier substrate forming a multi-chip module.

24. The semiconductor device of claim 19, wherein the semiconductor substrate element comprises a singulated semiconductor die having an area defined by a plurality of exposed sides of the semiconductor substrate element around an outside perimeter of the plurality of channels.

25. A computer system comprising:

an input device;

an output device;

a microprocessor and a cooperating memory coupled to the input device and the output device;

wherein at least one of the microprocessor and the memory comprises a semiconductor device comprising;

a carrier substrate having a plurality of terminal pads;

a semiconductor substrate, comprising;

a semiconductor element having an active surface bounded by an inside perimeter of a plurality of channels;

a plurality of bond pad over the active surface;

an intermediate conductive element associated with each of the plurality of bond pads and projecting from the active surface;

an encapsulant layer over at least the active surface of the semiconductor element and the plurality of channels, the intermediate conductive elements being exposed through the encapsulant layer, the intermediate conductive element exposure surface substantially conforming to a surface of the encapsulant layer;

depressions in the surface of the encapsulant layer over the channels; and

an external conductive element disposed over each of the intermediate conductive elements, the external conductive element contacting the intermediate conductive element at the exposure surface of the intermediate conductive element and projecting beyond the encapsulant layer;

wherein the external conductive elements are electrically connected to the terminal pads.