Chip scale packages performed by wafer level processing
First Claim
1. A semiconductor device comprising:
- a semiconductor element having an active surface bounded by an inside perimeter of a plurality of channels;
at least one bond pad over the active surface;
an intermediate conductive element associated with the at least one bond pad and projecting from the active surface;
an encapsulant layer over at least the active surface of the semiconductor element and the plurality of channels, the intermediate conductive element having a surface exposed through the encapsulant layer, the exposed surface substantially conforming to a surface of the encapsulant layer;
depressions in the surface of the encapsulant layer over the channels; and
an external conductive element disposed over the intermediate conductive element, the external conductive element contacting the intermediate conductive element at the exposed surface of the intermediate conductive element and projecting beyond the surface of the encapsulant layer.
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Accused Products
Abstract
Channels are formed that pass through an active surface of a semiconductor substrate to provide isolation between adjacent active surface regions defining individual die locations. Bond pads on the substrate are bumped with intermediate conductive elements, after which a material used to encapsulate the active surface is applied, filling the channels and covering exposed peripheral edges of the active surface integrated circuitry. The encapsulant is then planarized to expose the ends of the bumps. External conductive elements such as solder balls are then formed on the exposed bump ends. The semiconductor wafer is diced in alignment with the channels to singulate the semiconductor devices, the encapsulant in the channels keeping the edges of the integrated circuitry substantially hermetically sealed.
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Citations
25 Claims
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1. A semiconductor device comprising:
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a semiconductor element having an active surface bounded by an inside perimeter of a plurality of channels;
at least one bond pad over the active surface;
an intermediate conductive element associated with the at least one bond pad and projecting from the active surface;
an encapsulant layer over at least the active surface of the semiconductor element and the plurality of channels, the intermediate conductive element having a surface exposed through the encapsulant layer, the exposed surface substantially conforming to a surface of the encapsulant layer;
depressions in the surface of the encapsulant layer over the channels; and
an external conductive element disposed over the intermediate conductive element, the external conductive element contacting the intermediate conductive element at the exposed surface of the intermediate conductive element and projecting beyond the surface of the encapsulant layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A semiconductor device comprising:
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a semiconductor substrate element having an active surface bounded by an inside perimeter of a plurality of channels;
at least one bond pad over the active surface;
an intermediate conductive element associated with the at least one bond pad and extending over the active surface to a peripheral edge of the semiconductor substrate element; and
an encapsulant layer over at least the active surface of the semiconductor substrate element and the plurality of channels, the encapsulant layer leaving exposed an end portion of said intermediate conductive element substantially coplanar with a surface of the encapsulant layer on the peripheral edge of the semiconductor substrate element. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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19. A semiconductor device comprising:
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a semiconductor substrate element having an active surface bounded by an inside perimeter of a plurality of channels;
at least one bond pad over the active surface;
an intermediate conductive element associated with the at least one bond pad and projecting from the active surface an encapsulant layer over at least the active surface of the semiconductor substrate element and the plurality of channels, the encapsulant layer leaving exposed an end portion of the intermediate conductive element substantially coplanar with a surface of said encapsulant layer; and
an external conductive element disposed over the surface of the encapsulant layer, the external conductive element contacting the intermediate conductive element at the exposed end portion of the intermediate conductive element and extending therefrom over and in contact with the surface of the encapsulant layer to a peripheral edge of the semiconductor substrate element. - View Dependent Claims (20, 21, 22, 23, 24)
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25. A computer system comprising:
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an input device;
an output device;
a microprocessor and a cooperating memory coupled to the input device and the output device;
wherein at least one of the microprocessor and the memory comprises a semiconductor device comprising;
a carrier substrate having a plurality of terminal pads;
a semiconductor substrate, comprising;
a semiconductor element having an active surface bounded by an inside perimeter of a plurality of channels;
a plurality of bond pad over the active surface;
an intermediate conductive element associated with each of the plurality of bond pads and projecting from the active surface;
an encapsulant layer over at least the active surface of the semiconductor element and the plurality of channels, the intermediate conductive elements being exposed through the encapsulant layer, the intermediate conductive element exposure surface substantially conforming to a surface of the encapsulant layer;
depressions in the surface of the encapsulant layer over the channels; and
an external conductive element disposed over each of the intermediate conductive elements, the external conductive element contacting the intermediate conductive element at the exposure surface of the intermediate conductive element and projecting beyond the encapsulant layer;
wherein the external conductive elements are electrically connected to the terminal pads.
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Specification