Integrated circuit testing with a visual indicator

• US 6,717,430 B2
• Filed: 02/13/2002
• Issued: 04/06/2004
• Est. Priority Date: 02/13/2002
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Burch, Kenneth R.
• Primary Examiner(s): WILCZEWSKI, MARY A
• Application Number:
  US10/075,047
• Publication Number:
  US 20030153105A1
• Time in Patent Office: 783 Days
• Field of Search: 324/765, 324/766, 324/767, 324/768, 324/769, 324/770, 438/17, 438/18
• US Class Current: 324/750.18
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

Wafer level testing is accomplished by using a visual indicator (43) in lieu of a probe machine. Before singulation, each die (52) in a wafer (50) is placed into a test mode and BIST circuitry (39) in each die performs predetermined tests of the other circuits on the die. A pass/fail signal is communicated to a visual indicating device, such as an LED, on the wafer. Each die has a corresponding visual indicator. The LED may be contained either on the die or in the scribe area. Multiple LEDs may be used for multiple circuit modules under test. The test permits easy detection of failures without using probing. Testing such as burn-in may be performed to determine whether a part will survive a range of operating conditions. In one form, a CMOS implementation of an LED may be used in conjunction with a CMOS wafer.

Claims

1. A method for testing an integrated circuit, comprising:

providing a wafer having multiple die that are separated by a singulation area and each containing the integrated circuit;

providing a visual functional indicator for some or all of the multiple die, the visual functional indicator indicating functionality of multiple circuit modules of an associated die and is contained on or adjacent to the associated die;

providing test circuitry on each of the some or all of the multiple die, the test circuitry being dedicated specifically for testing an associated one of the some or all of the multiple die that have a visual functional indicator in response to receiving a test enable signal at an input pad thereof;

powering up the wafer to electrically activate the multiple die and initiate operation of the test circuitry;

performing predetermined tests with the test circuitry for the some or all of the multiple die;

outputting a test result to the visual functional indicator for each of the some or all of the multiple die;

using the test result to create a visual indication on or adjacent the some or all of the multiple die with each visual functional indicator corresponding to the test result; and

recording the visual functional indicator for each of the some or all of the multiple die on or after a fixed predetermined time after receiving the test enable signal.

2. The method of claim 1 further comprising:

physically locating a single visual functional indicator within each of the some or all of the multiple die.

3. The method of claim 1 further comprising:

physically locating the visual functional indicator external to the some or all of the multiple die and within a scribe area of the wafer.

4. The method of claim 1 further comprising:

implementing the visual functional indicator as a light indicating device that provides a predetermined code value indicative of the test result.

5. The method of claim 1 further comprising:

providing a single visual functional indicator for each of the some or all of the multiple die and sequentially testing multiple modules of each of the some or all of the multiple die and sequentially indicating a test result for the multiple modules with the single visual indicator.

6. The method of claim 1 further comprising:

resetting the test circuitry to an initial state in response to powering up the wafer.

7. The method of claim 1 further comprising:

singulating the multiple die and segregating functional die of the multiple die from non-functional die of the multiple die based upon the visual indication.

8. A method for testing an integrated circuit comprising:

providing a wafer having multiple die that are separated by a singulation area;

providing a visual functional indicator for each of some or all of the multiple die;

providing test circuitry for each of the some or all of the multiple die that have a visual functional indicator;

powering up the wafer to electrically activate the multiple die and initiate operation of the test circuitry;

performing predetermined tests with the test circuitry for the some or all of the multiple die;

outputting a test result to the visual functional indicator for the some or all of the multiple die;

using the test result to create a visual indication on the wafer with each visual functional indicator corresponding to the test result; and

implementing the visual functional indicator as a binary coded decimal (BCD) light emitting diode (LED) that asserts a predetermined decimal upon passing a corresponding predetermined functional test.

9. A method for testing an integrated circuit comprising:

providing a wafer having multiple die that are separated by a singulation area;

providing a visual functional indicator for each of some or all of the multiple die;

providing test circuitry for each of the some or all of the multiple die that have a visual functional indicator;

powering up the wafer to electrically activate the multiple die and initiate operation of the test circuitry;

performing predetermined tests with the test circuitry for the some or all of the multiple die;

outputting a test result to the visual functional indicator for the some or all of the multiple die;

using the test result to create a visual indication on the wafer with each visual functional indicator corresponding to the test result; and

recording the visual indication with either a camera or a high resolution imager to form a data base that is used by a singulation tool to singulate the multiple die and segregate the multiple die based on the visual indication.

10. A method for testing an integrated circuit, comprising:

providing a wafer having multiple die that are separated by a singulation area;

providing a visual functional indicator for multiple functional modules of each of the multiple die thereby providing a plurality of visual indicators distributed across the wafer;

providing a dedicated built-in self-test (BIST) circuit for each of the multiple die;

powering up the wafer to electrically activate the multiple die and initiate operation of the built-in self-test (BIST) circuit;

performing predetermined tests with the test circuitry for each of the multiple die;

outputting a test result to the visual functional indicator for each of the multiple die; and

using the test result to create a visual indication on the wafer with each visual functional indicator corresponding to the test result and providing a predetermined value indicative of the test result.

11. The method of claim 10 further comprising:

using a portion of the plurality of visual indicators for both a test mode of operation and a normal functional mode of operation.

12. The method of claim 10 further comprising:

positioning each respective visual functional indicator within a corresponding respective one of the multiple die.

13. The method of claim 10 further comprising:

implementing each visual functional indicator with a light emitting diode (LED).

14. A method for testing an integrated circuit, comprising:

providing a wafer having multiple die;

providing a visual functional indicator for each of a plurality of the multiple die;

coupling dedicated test circuitry to the visual functional indicator in each of the multiple die that have a visual functional indicator;

powering up the wafer to electrically activate the multiple die and initiate operation of the test circuitry;

enabling the test circuitry with an enable signal applied to an input of each of the plurality of the multiple die;

performing predetermined tests with the test circuitry for each of the plurality of the multiple die;

outputting a test result to each visual functional indicator to visually indicate which die of the multiple die passed the predetermined tests and which die failed the predetermined tests; and

using imaging means to inspect each visual functional indicator and record test results.

15. The method of claim 14 further comprising:

physically locating each functional indicator within a scribe area of the wafer.

16. A method for testing an integrated circuit comprising:

providing a wafer having multiple die;

providing a visual functional indicator for each of the multiple die;

providing test circuitry for each of the multiple die that have a visual functional indicator;

powering up the wafer to electrically activate the multiple die and initiate operation of the test circuitry;

performing predetermined tests with the test circuitry for the multiple die;

outputting a test result to each visual functional indicator to visually indicate which die of the multiple die passed the predetermined tests and which die failed the predetermined tests; and

recording each visual functional indicator with either a camera or a high resolution imager to form a data base that is used by a singulation tool to singulate the multiple die and segregate the multiple die based on each visual functional indicator.