High-speed differential to single-ended converter

• US 6,717,474 B2
• Filed: 04/02/2002
• Issued: 04/06/2004
• Est. Priority Date: 01/28/2002
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: Integrated Programmable Communications, Inc.
• Inventors: Chen, Yi-Huei, Huang, Po-Chiun
• Primary Examiner(s): Nguyen, Khanh V.
• Application Number:
  US10/115,179
• Publication Number:
  US 20030141935A1
• Time in Patent Office: 735 Days
• Field of Search: 330/253, 330/255, 330/257, 330/301
• US Class Current: 330/301
• CPC Class Codes: H03F 3/45206 Folded cascode stages

Abstract

A differential to single-ended converter, which is composed of a transconductance amplifier, a current mirror and buffer circuit and a transimpedance stage, is disclosed. A differential voltage signal is provided to the inputs of the transconductance amplifier and converted to a differential current signal. The current mirror and buffer circuit serves as a differential to single-ended current conveyer and isolates the transconductance stage and the following transimpedance stage. Finally, the single-ended current signal is provided to the input of the transimpedance stage and converted to a single-ended current signal.

Claims

1. A differential, to single-ended converter comprising:

a transconductance amplifier for receiving a differential voltage signal and converting the differential voltage signal to a differential current signal, wherein the transconductance amplifier has a degeneration resistor;

a current mirror and buffer circuit, coupled to the transconductance amplifier, for conveying the differential current signal to a single-ended current signal; and

a transimpedance amplifier, coupled to the current mirror and buffer circuit, for receiving the single-ended current signal and converting the single-ended current signal to a single-ended voltage signal, wherein the transimpedance amplifier has a shunt feedback resistor;

wherein the current mirror and buffer circuit provides isolation between the transconductance amplifier and the transimpedance amplifier, and an overall gain of the differential to single-ended converter is determined by a ratio of resistance values of the degeneration resistor and the shunt feedback resistor.

2. The differential to single-ended converter an recited in claim 1, wherein the current mirror and buffer circuit comprises:

first and second MOS transistors having gates receiving a bias voltage, having sources coupled to a second supply node, and having drains receiving the differential current signal;

third and fourth MOS transistors having gates receiving the bias voltage and having sources coupled to the drains of the first and second MOS transistors, respectively;

a fifth MOS transistor having a drain and a gate coupled to a drain of the third MOS transistor and having a source coupled to a first supply node; and

a sixth MOS transistor having a gate coupled to the drain of the third MOS transistor, having a source coupled to the first supply node and having a drain coupled to a drain of the fourth MOS transistor and providing the single-ended current signal.

3. A differential to single-ended converter comprising:

a transconductance amplifier for receiving a differential voltage signal and converting the differential voltage signal to a differential current signal, the transconductance amplifier having

first and second MOS transistors for receiving the differential voltage signal at their gates and providing the differential voltage signal at their drains,

a degeneration resistor coupled between sources of the first and second MOS transistor, and

third and fourth MOS transistors having drains coupled to the sources of the first and second transistors, having sources coupled to a first supply node and having gates receiving a bias voltage;

a current mirror and buffer circuit, coupled to the transconductance amplifier, for conveying the differential current signal to a single-ended current signal; and

a transimpedance amplifier, coupled to the current mirror and buffer circuit, for receiving the single-ended current signal and converting the single-ended current signal to a single-ended voltage signal;

wherein the current mirror and buffer circuit provides isolation between the transconductance amplifier and the transimpedance amplifier.

4. A differential to single-ended converter comprising:

a transconductance amplifier for receiving a differential voltage signal and converting the differential voltage signal to a differential current signal;

a current mirror and buffer circuit, coupled to the transconductance amplifier, for conveying the differential current signal to a single-ended current signal; and

a transimpedance amplifier, coupled to the current mirror and buffer circuit, for receiving the single-ended current signal and converting the single-ended current signal to a single-ended voltage signal, the transimpedance having

a first MOS transistor having a gate receiving the single-ended current signal and having a source coupled to a second supply node;

a second MOS transistor having a gate coupled to the gate of the first MOS transistor, having a source coupled to a first supply node, and having a drain coupled to a drain of the first MOS transistor for providing the single-ended voltage signal; and

a shunt feedback resistor coupled between the gates and the drains of the first and second MOS transistors.

5. A differential to single-ended converter, comprising:

first and second supply nodes;

first and second MOS transistors having gates receiving a differential input signal;

a degeneration resistor coupled between sources of the first and second MOS transistors;

third and fourth MOS transistors having drains coupled to the sources of the first and second transistors, having sources coupled to the first supply node and having gates receiving a bias voltage;

fifth and sixth MOS transistors having gates receiving the bias voltage, having sources coupled to the second supply node, and having drains coupled to drains of the first and second MOS transistors, respectively;

seventh and eight MOS transistors having gates receiving the bias voltage and having sources coupled to the drains of the first and second MOS transistors, respectively;

ninth and tenth MOS transistors having drains coupled to drains of the seventh and eighth MOS transistors, respectively, having gates coupled to the drain of the ninth MOS transistor and having sources coupled to the first supply node;

an eleventh MOS transistor having a gate coupled to the drain of the tenth MOS transistor and having a source coupled to the second supply node;

a twelfth MOS transistor having a gate coupled to the drain of the tenth MOS transistor, having a source coupled to the first supply node, and having a drain coupled to a drain of the eleventh MOS transistor, and

a shunt feedback resistor coupled between the gates and the drains of the eleventh and twelfth MOS transistors;

wherein a single-ended output signal is provided by the connected drains of the eleventh and twelfth MOS transistors.

6. The differential to single-ended converter as recited in claim 5, wherein the first and second MOS transistors, the third and fourth MOS transistors, the ninth and tenth MOS transistors and the twelfth MOS transistor are PMOS transistors;

and the fifth and sixth MOS transistors, the seventh and eighth MOS transistors and the eleventh MOS transistor are NMOS transistors.

7. The differential to single-ended converter as recited in claim 6, an overall gain of the differential to single-ended converter is determined by a ratio of resistance values of the degeneration resistor and the shunt feedback resistor.