Coil and coil system for integration into a micro-electronic circuit and microelectronic circuit

• US 6,717,503 B2
• Filed: 07/22/2002
• Issued: 04/06/2004
• Est. Priority Date: 01/20/2000
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Tiebout, Marc, Sewald, Dieter, Berthold, Jörg
• Primary Examiner(s): Mai, Anh T.
• Application Number:
  US10/200,422
• Publication Number:
  US 20030034867A1
• Time in Patent Office: 624 Days
• Field of Search: 336/200, 336/223, 336/232
• US Class Current: 336/200
• CPC Class Codes: H01F 17/0033 with the coil helically wound around a magnetic core
• CPC Class Codes: H01F 27/36 Electric or magnetic shields or screens movable for varying inductance H01F21/10
• CPC Class Codes: H01F 27/363 made of electrically conductive material
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

The coil and coil system is provided for integration in a microelecronic circuit. The coil is placed inside an oxide layer of a chip, and the oxide layer is placed on the substrate surface of a substrate. The coil comprises one or more windings, whereby the winding(s) is/are formed by at least segments of two conductor tracks, which are each provided in spatially spaced-apart metalization levels, and by via-contacts which connect these conductor track(s) and/or conductor track segments. In order to be able to produce high-quality coils, a coil is produced with the largest possible coil cross-section, whereby a standard metalization, especially a standard metalization using copper, can, however, be used for producing the oil. To this end, the via contacts are formed from a stack of two ore more via elements arranged one above the other. Parts of the metalization levels can be located between the via elements.

Claims

1. A coil for integration into a microelectronic circuit on a chip, comprising:

interconnects formed in spatially separate metalization planes of the chip;

at least one turn formed by said interconnects formed in the spatially separate metalization planes and via contacts connecting said interconnects, each via contact being formed from a stack of at least two via elements disposed one above the other.

2. The coil according to claim 1, wherein said interconnects are formed in segments and said at least one turn is formed by said segments of said interconnects.

3. The coil according to claim 2, wherein the coil has a defined cross section delimited by said segments of said interconnects and said via contacts.

4. The coil according to claim 2, wherein at least one component selected from the group consisting of said interconnects, said interconnect segments, and said via elements is formed of copper.

5. The coil according to claim 4, wherein said copper is electrolytically deposited copper.

6. The coil according to claim 1, wherein constituent parts of a metalization plane are disposed at least between individual said via elements of a respective stack.

7. The coil according to claim 6, wherein at least one component selected from the group consisting of said interconnects, said interconnect segments, and said via elements, and said constituent parts of the metalization plane between individual via elements is formed of copper.

8. The coil according to claim 7, wherein said copper is electrolytically deposited copper.

9. The coil according to claim 1, wherein at least one component selected from the group consisting of said interconnects and said via elements is formed of copper.

10. The coil according to claim 9, wherein said copper is electrolytically deposited copper.

11. The coil according to claim 1, wherein said via contacts extend substantially perpendicular to said interconnects.

12. The coil according to claim 1, wherein the coil has a defined cross section delimited by said interconnects and said via contacts.

13. The coil according to claim 1, wherein said interconnects forming said at least one turn are disposed at a spacing distance of approximately 4 μ

m from one another.

14. The coil according to claim 1 configured for integration in a microelectronic circuit disposed on and/or in a substrate, wherein a coil axis is oriented horizontally with respect to the substrate surface.

15. The coil according to claim 1, wherein said turns define a coil start and a coil end of the coil and said coil start and said coil end are disposed adjacent one another, such that a coil axis forms an at least approximately closed line.

16. The coil according to claim 15, wherein the coil axis forms a substantially circular line.

17. A coil system for a micro-electronic circuit, comprising at least one coil according to claim 1 integrated in the micro-electronic circuit.

18. The coil system according to claim 17, which comprises a plurality of via stacks for shielding the at least one coil each formed of a number of via stacks each formed from at least two via elements, and wherein said via stacks are disposed outside the at least one coil.

19. The coil system according to claim 18, wherein said via stacks are formed outside a coil periphery, around said coil.

20. The coil system according to claim 18, wherein said via stacks are oriented approximately perpendicularly to a coil axis.

21. A microelectronic circuit, comprising a number of integrated components, said integrated components including an inductance formed as a coil system according to claim 17.

22. The microelectronic circuit according to claim 21, wherein said integrated components and said coil system are integrated in a chip, and said chip is formed from a substrate and at least one oxide layer.

23. The microelectronic circuit according to claim 22, wherein said coil system is arranged within said oxide layer.

24. The coil system according to claim 17, which comprises at least one shielding plane for vertically shielding the coil.

25. The coil system according to claim 24, wherein said shielding plane is a metal plane.

26. The coil system according to claim 24, wherein said shielding plane is a polysilicon plane.

27. The coil system according to claim 24, wherein said shielding plane is a structure with a highly doped substrate.

28. A microelectronic circuit, comprising a number of integrated components, said integrated components including an inductance formed as a coil according to claim 1.

29. The microelectronic circuit according to claim 28, wherein said integrated components and said coil are integrated in a chip, and said chip is formed from a substrate and at least one oxide layer.

30. The microelectronic circuit according to claim 29, wherein said coil is arranged within said oxide layer.