Multiple temperature threshold sensing having a single sense element

• US 6,717,530 B1
• Filed: 08/14/2000
• Issued: 04/06/2004
• Est. Priority Date: 08/30/1999
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Marshall, Andrew, Xu, Jingwei, Schmidt, Thomas A.
• Primary Examiner(s): Horabik, Michael
• Assistant Examiner(s): DANG, HUNG Q
• Application Number:
  US09/638,839
• Time in Patent Office: 1,331 Days
• Field of Search: 340/870.17, 340/870.16, 327/12, 327/513, 327/3, 327/7, 327/115, 327/101, 702/132, 702/130, 702/131, 324/760
• US Class Current: 340/870.17
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A temperature sensing system (30) that providing at least one detect signal related to temperature in an integrated circuit is presented. This system uses one thermal sensing circuit (40) to detect two or more temperature thresholds (t₂, t₃) and differentiates the temperature thresholds using time multiplexed logic control. The system (80) capable of detecting more than two temperatures includes the thermal sensing circuit (90) and a decode circuit (92) with at least one detect latch (100). Optionally, the system may include a hysteresis circuit (60). The thermal sensing circuit (40), connected to the integrated circuit, generates a detect signal (D₄) in response to the a temperature selection signal (T₁). This flexible on-board temperature monitoring solution reduces the cost of thermal feedback sensing by reducing die area and improves the correlation of detected temperatures. In addition, this solution reduces the possibility of mismatch and tracking errors between two or more sense elements.

Claims

1. A thermal sensing system for an integrated circuit comprising:

a thermal sensing circuit, having a first input for a voltage bias and a second input for a temperature selection clock signal T₁, the thermal sensing circuit for monitoring the temperature t₀ of the integrated circuit for a temperature in between a first t₁ and a second t₂ threshold temperature range, wherein if t₁≦

t₀≦

t₂, the thermal sensing circuit generates at least one detection signal;

a decode circuit, having a first input, a second input, a first detect latch output, and a second detect latch output, the decode circuit coupled to the thermal sensing circuit for receiving the at least one detection signal to determine whether the first t₁ and second t₂ threshold temperature has been reached and generating at least one detection flag signal at a predetermined threshold temperature, the first input coupled to receive the temperature selection clock signal T₁, the second input coupled to receive the a detection clock signal C₁, wherein the detection clock signal C₁ has a higher frequency than that of the temperature selection clock signal T₁; and

a hysteresis circuit coupled to the first and second detect latch outputs for receiving the at least one detection flag and generating a shutdown signal to selectively reduce the power consumption of the integrated circuit to prevent overheating.

2. The thermal sense system according to claim 1, wherein the thermal sense circuit includes

a current source;

a multiple output current mirror having an input lead and at least three output leads, the input lead coupled to the current source;

a MOSFET transistor having a gate, a source and a drain, the source coupled to the first output of the multiple output current mirror for receiving current;

a bipolar transistor having a base, collector, and emitter, the base coupled to the second output of the multiple output current mirror and drain of the MOSFET transistor, the collector coupled to the third output of the multiple output current mirror;

a resistor coupled between the base of the bipolar transistor and ground; and

an inverting output driver for generating the detection signal, the inverting output driver coupled to the collector of the bipolar transistor.

3. The thermal sense circuit according to claim 2, wherein the multiple output current mirror having an input and three outputs includes

a first MOS transistor having a source, drain and gate, the source coupled to the power supply rail, the drain and gate coupled to the input of the multiple output current mirror;

a second MOS transistor having a source, drain and gate, the source coupled to the power supply rail, the drain coupled to the first output of the multiple output current mirror, the gate coupled to the gate of the first MOS transistor;

a third MOS transistor having a source, drain and gate, the source coupled to the power supply rail, the drain coupled to the second output of the multiple output current mirror, the gate coupled to the gate of the first MOS transistor; and

a fourth MOS transistor having a source, drain and gate, the source coupled to the power supply rail, the drain coupled to the third output of the multiple output current mirror, the gate coupled to the gate of the first MOS transistor.

4. The thermal sense circuit according to claim 2, wherein the inverting output driver includes

a first MOS transistor having a source, drain and gate, the source coupled to the power supply rail and

a second MOS transistor having a source, drain and gate, the source coupled to ground, the gate coupled to the gate of the first MOS transistor, the drain coupled to the drain of the first MOS transistor to form a detection signal node.

5. The thermal sensing system according to claim 1, wherein the decode circuit includes

a first and second NAND gate, each NAND gate having at least two inputs and at least one output, the first input of the first NAND gate coupled to the detection clock signal, the second input of the first NAND gate coupled to the temperature selection clock signal, the first input of the second NAND gate coupled to the first input of the first NAND gate;

a first inverter having an input and an output, the input coupled to the temperature selection signal, the output coupled as the second input of the second NAND gate;

a second and third inverter each having an input and an output, the input of the second inverter coupled to the output of the first NAND gate, the input of the third inverter coupled to the output of the second NAND gate; and

a first and a second flip-flop register each having a clocking input, an signal input and an output for generating a detection flag signal, the clocking input of the first flip-flop register coupled to the output of the second inverter, the signal input of the first flip-flop register coupled to the detection signal, the clocking input of the second flip-flop register coupled to the output of the third inverter, the signal input of the second flip-flop register coupled to the detection signal.

6. The thermal sensing system according to claim 1, wherein the hysteresis circuit includes:

a first inverter having an input and an output, the input coupled to the output of the first flip-flop register to receive the detection flag signal of the first flip-flop register;

a first NOR gate having at least two inputs and one output, the first input coupled to the output of the second flip-flop register to receive the detection flag signal of the first flip-flop register;

a second NOR gate having at least two inputs and one output, the first input coupled to the output of the first inverter, the second input coupled to the output of the first NOR gate; and

a third flip-flop register having a clocking input, an signal input and an output for generating a shutdown signal, the clocking input coupled to receive the temperature selection signal, the signal input coupled to receive the output of second NOR gate, the output coupled to the second input of the first NOR gate.

7. A thermal sensing system for an integrated circuit comprising:

a thermal sensing circuit coupled to receive at least two temperature selection signals of predetermined threshold temperatures and bias current for monitoring the temperature of the integrated circuit and generating at least one detection signal;

a decoder for decoding the temperature selection signals coupled to receive the temperature selection signals and generating decoded temperature selection signals; and

a decode circuit coupled to said thermal sensing circuit for receiving the at least one detection signal, the decoded temperature selection signals, and a detection clocking signal, the decode circuit for generating corresponding detection flag signals at the predetermined threshold temperatures.

8. The thermal sense system according to claim 7, wherein the thermal sense circuit includes:

a current source;

a multiple output current mirror having an input lead and at least four output leads, the input lead coupled to the first current mirror;

a first and second MOS transistor having a gate, a source and a drain, the source of the first MOS transistor coupled to the first output of the multiple output current mirror for receiving current, the source of the second MOS transistor coupled to the second output of the multiple output current mirror for receiving current, gate of the first MOS transistor coupled to receive the first temperature selection signal, gate of the second MOS transistor coupled to receive the second temperature selection signal;

a bipolar transistor having a base, collector, and emitter, the base coupled to the third output of the multiple output current mirror and drain of the first and second MOS transistors, the collector coupled to the fourth output of the multiple output current mirror;

a resistor coupled between the base of the bipolar transistor and ground; and

an inverting output driver for generating the detection signal, the inverting output driver coupled to the collector of the bipolar transistor.

9. The thermal sense circuit according to claim 8, wherein the multiple output current mirror having an input and at least four outputs includes

a first MOS transistor having a source, drain and gate, the source coupled to the power supply rail, the drain and gate coupled to the input of the multiple output current mirror;

a second MOS transistor having a source, drain and gate, the source coupled to the power supply rail, the drain coupled to the first output of the multiple output current mirror, the gate coupled to the gate of the first MOS transistor;

a third MOS transistor having a source, drain and gate, the source coupled to the power supply rail, the drain coupled to the second output of the multiple output current mirror, the gate coupled to the gate of the first MOS transistor;

a fourth MOS transistor having a source, drain and gate, the source coupled to the power supply rail, the drain coupled to the third output of the multiple output current mirror, the gate coupled to the gate of the first MOS transistor; and

a fifth MOS transistor having a source, drain and gate, the source coupled to the power supply rail, the drain coupled to the fourth output of the multiple output current mirror, the gate coupled to the gate of the first MOS transistor.

10. The thermal sense circuit according to claim 8, wherein the inverting output driver includes

a first MOS transistor having a source, drain and gate, the source coupled to the power supply rail and

a second MOS transistor having a source, drain and gate, the source coupled to ground, the gate coupled to the gate of the first MOS transistor, the drain coupled to the drain of the first MOS transistor to form a detection signal node.

11. The thermal sensing system according to claim 8, wherein the decode circuit includes:

a first, second, third and fourth NAND gate, each NAND gate having at least two inputs and at least one output, each NAND gate having the first input coupled to the detection clock signal, the second input of the first NAND gate coupled to the first decoded temperature selection signal, the second input of the second NAND gate coupled to the second decoded temperature selection signal, the second input of the third NAND gate coupled to the third decoded temperature selection signal, the second input of the fourth NAND gate coupled to the fourth decoded temperature selection signal, the first input of the second NAND gate coupled to the first input of the first NAND gate;

a first, second, third and fourth inverter having an input and an output, the input of the first inverter coupled to the output of the first NAND gate, the input of the second inverter coupled to the output of the second NAND gate, the input of the third inverter coupled to the output of the third NAND gate, the input of the fourth inverter coupled to the output of the fourth NAND gate; and

a first, second, third and fourth flip-flop register each having a clocking input, an signal input and an output for generating a detection flag signal, each flip-flop register having the signal input coupled to the detection signal node, the clocking input of the first flip-flop register coupled to the output of the first inverter, the clocking input of the second flip-flop register coupled to the output of the second inverter, the clocking input of the third flip-flop register coupled to the output of the third inverter, the clocking input of the fourth flip-flop register coupled to the output of the fourth inverter.