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Non-volatile semiconductor memory having split-gate memory cells mirrored in a virtual ground configuration

  • US 6,717,846 B1
  • Filed: 10/26/2000
  • Issued: 04/06/2004
  • Est. Priority Date: 11/24/1999
  • Status: Expired due to Term
First Claim
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1. A non volatile memory, comprising:

  • a) flash memory cells organized in rows and columns, b) cells in a row are interconnected by a wordline connecting to control gates of said flash memory cells in said row, c) cell layout in a column mirrors cell layout in adjacent columns producing a first pair of adjacent columns with drains close together and a second pair of adjacent columns with sources close together, d) a bit line extend full length of said columns, laying between said first pair of adjacent columns and connecting said drains of said first pair of adjacent columns to a sense amplifier, e) a source line extend full length of said columns, laying between said second pair of adjacent columns and connecting said sources of said second pair of adjacent columns to source voltages, f) a program operation of said flash memory cells organized by a vertical page associated with said source line whereby a source line voltage and a bit line voltage of said vertical page are set for said program operation and a wordline program voltage is stepped from cell to cell, g) an erase operation of said flash memory cells organized by horizontal block whereby all bit lines, source lines and word lines are coupled to a same voltage and then wordlines coupled to cells to be erased are biased to an erase voltage.

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