Non-volatile semiconductor memory having split-gate memory cells mirrored in a virtual ground configuration

• US 6,717,846 B1
• Filed: 10/26/2000
• Issued: 04/06/2004
• Est. Priority Date: 11/24/1999
• Status: Expired due to Term

• Current Assignee: Foothills IP LLC
• Original Assignee: Aplus Flash Technology, Inc.
• Inventors: Chen, Hung-Sheng, Chan, Vei-Han, Lee, Peter W.
• Primary Examiner(s): Tran, Andrew Q.
• Application Number:
  US09/696,085
• Time in Patent Office: 1,258 Days
• Field of Search: 365/185.16, 365/185.18, 365/185.19, 365/185.02, 365/185.11, 365/185.12, 365/185.33
• US Class Current: 365/185.02
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

In this invention a process for a flash memory cell and an architecture for using the flash memory cell is disclosed to provide a nonvolatile memory having a high storage density. Adjacent columns of cells share the same source and the source line connecting these sources runs vertically in the memory layout, connecting to the sources of adjacent columns memory cells. Bit lines connect to drains of cells in adjacent columns and are laid out vertically, alternating with source lines in an every other column scheme. Wordlines made of a second layer of polysilicon form control gates of the flash memory cells and are continuous over the full width of a memory partition. Programming is done in a vertical page using hot electrons to inject charge onto the floating gates. The cells are crased using Fowler-Nordheim tunneling of electrons from the floating gate to the control gate by way of inter polysilicon oxide formed on the walls of the floating gates.

Claims

1. A non volatile memory, comprising:

a) flash memory cells organized in rows and columns,

b) cells in a row are interconnected by a wordline connecting to control gates of said flash memory cells in said row,

c) cell layout in a column mirrors cell layout in adjacent columns producing a first pair of adjacent columns with drains close together and a second pair of adjacent columns with sources close together,

d) a bit line extend full length of said columns, laying between said first pair of adjacent columns and connecting said drains of said first pair of adjacent columns to a sense amplifier,

e) a source line extend full length of said columns, laying between said second pair of adjacent columns and connecting said sources of said second pair of adjacent columns to source voltages,

f) a program operation of said flash memory cells organized by a vertical page associated with said source line whereby a source line voltage and a bit line voltage of said vertical page are set for said program operation and a wordline program voltage is stepped from cell to cell,

g) an erase operation of said flash memory cells organized by horizontal block whereby all bit lines, source lines and word lines are coupled to a same voltage and then wordlines coupled to cells to be erased are biased to an erase voltage.

2. The non volatile memory of claim 1 wherein, said wordlines are polysilicon lines laying over floating gates of said flash memory cells in said row and forming control gates for said flash memory cells.

3. The non volatile memory of claim 1 wherein, said vertical page programming is done to cells in a selected column where the source line of said selected column is biased to a high positive voltage, the bit line of said selected column is biased to zero volts and the wordline of a selected cell in said selected column is biased to a positive voltage approximately equal to a threshold voltage of said flash memory cells with all other wordlines biased to zero volts and the bit line of said adjacent column of cells sharing said source line to a moderate positive voltage.

4. The non volatile memory of claim 1 wherein, horizontal page or block erase is done in one or more rows of said flash memory cells by setting all bit lines, source lines and wordlines to zero volts, and applying a high positive voltage to the wordlines of the one or more rows to be erased.

5. The non volatile memory of claim 1 wherein, said flash memory cells are read by applying zero volts to the source line connected to a cell to be read, applying a positive voltage to the bit line connected to the cell to be read, applying Vcc to the word line of the cell to be read, setting all other bit lines and source lines to said positive voltage, and setting all other wordlines to zero volts.