Selective operation of a multi-state non-volatile memory system in a binary mode

• US 6,717,847 B2
• Filed: 08/26/2002
• Issued: 04/06/2004
• Est. Priority Date: 09/17/2001
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Chen, Jian
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US10/229,258
• Publication Number:
  US 20030053334A1
• Time in Patent Office: 589 Days
• Field of Search: 365/185.03, 365/185.12, 365/185.24, 365/230.03, 365/184
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A flash non-volatile memory system that normally operates its memory cells in multiple storage states is provided with the ability to operate some selected or all of its memory cell blocks in two states instead. The two states are selected to be the furthest separated of the multiple states, thereby providing an increased margin during two state operation. This allows faster programming and a longer operational life of the memory cells being operated in two states when it is more desirable to have these advantages than the increased density of data storage that multi-state operation provides.

Claims

1. A method of controllably operating a plurality of blocks of erasable and re-programmable non-volatile memory cells in either at least four threshold level states or exactly two threshold level states, wherein said at least four threshold level states are spaced apart across a memory cell operating threshold window and said exactly two threshold level states are those of the at least four threshold level states that are maximally separated from each other within the operating threshold window, thereby to provide an increased margin between said two threshold level states maximally separated from each other.

2. The method of claim 1, wherein the memory cells within at least one of the plurality of blocks is operated in said exactly two threshold level states and the memory cells within at least another one of the plurality of blocks is operated in said at least four threshold level states.

3. The method of claim 2, wherein a table of blocks of memory in which user data are stored is written into memory cells of said at least one of the plurality of blocks that is operated in said exactly two threshold levels, and the user data is stored in memory cells of said at least another one of the plurality of blocks that is operated in said at least four threshold level states.

4. The method of claim 1, wherein at least one of said plurality of blocks of memory cells is initially operated in said at least four threshold level states until a number of erase/programming cycles of said at least one block reaches a predetermined amount, upon which said at least one block is then operated in said at least two threshold level states.

5. In a memory system having a plurality of blocks of non-volatile memory cells that individually stores more than one bit of data in one of more than two threshold level distributions that are spaced apart across an operating threshold window, a method of operating the memory system comprising storing one bit of data in the memory cells of at least one of the blocks in only two of said more than two threshold level distributions that are furthest displaced from each other within the operating threshold window.

6. The method of claim 5, which additionally comprises reading data from the individual cells of said at least some of the blocks that are stored in said only two of the more than two threshold level distributions by use of a threshold reference having a value intermediate of the two threshold level distributions furthest displaced from each other.

7. The method of claim 6, wherein one of said only two threshold level distributions furthest displaced from each other is an erased distribution within a negative region of the operating threshold window and said read threshold reference is a non-zero positive voltage.

8. The method of claim 5, wherein the memory system is a NAND system.

9. A method of operating a memory system including an array of non-volatile memory cell transistors having storage elements that individually store charge in one of a given number of at least four non-overlapping charge level ranges with a multi-state margin therebetween in order to store therein at least two bits of data being programmed, comprising selectively programming charge levels of the storage elements of a portion of the array of memory cell transistors into ranges less than said given number with a margin therebetween that is in excess of said multi-state margin and extends across charge levels occupied by others of said given number of charge level ranges therebetween.

10. The method of claim 9, additionally comprising maintaining a usage count for at least said portion of the array, and wherein programming said portion of the array includes initially programming the storage elements of said portion of the array into said given number of charge level ranges until the usage count exceeds a predetermined amount, upon which the storage elements of said portion are thereafter programmed into said less than said given number of charge level ranges.

11. A memory system, comprising:

a plurality of non-volatile memory cell transistors having erasable and re-programmable charge storage elements, and

programming circuits that control charge levels stored on the charge storage elements to be within either (1) a given number of at least four non-overlapping ranges to store at least two bits of data per charge storage element or (2) within a minimum and maximum of said given number of ranges to store only one bit of data per charge storage element and having a margin therebetween extending across intervening ranges between the minimum and maximum of said given number of ranges.

12. The memory system of claim 11, wherein the plurality of memory cell transistors include a plurality of series strings of at least eight memory cell transistors that extend in one direction across a semiconductor substrate between bit lines and a voltage source, and word lines extending across the strings in a second direction across the substrate, the first and second directions being orthogonal to each other, the charge storage elements being located within the strings of memory cell transistors where crossed by the word lines.

13. The memory system of claim 12, wherein the array of a plurality of memory cell transistors are organized into erase units of a minimum number of memory cell transistors that are erasable together, the programming circuits controlling charge levels stored on all the charge storage elements within the individual erase units to be either within (1) said given number or (2) said minimum and maximum levels of said given number.

14. The memory system of claim 13, wherein the charge storage elements are electrically conductive floating gates.