SRAM power-up system and method

• US 6,717,867 B2
• Filed: 01/21/2003
• Issued: 04/06/2004
• Est. Priority Date: 12/21/2001
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Marr, Ken W.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): PHAM, LY D
• Application Number:
  US10/349,462
• Publication Number:
  US 20030128595A1
• Time in Patent Office: 441 Days
• Field of Search: 365/154, 365/156, 365/189.09, 365/202, 365/226, 365/195, 365/196, 365/188, 365/189.11
• US Class Current: 365/189.09
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Abstract

A power-up circuit for an SRAM, particularly a loadless 4-T SRAM cell having PMOS access transistors. The power-up circuit disables a current path to the digit lines in an array of SRAM cells during power-up of the SRAM. As a result, the SRAM cells cannot draw power from the digit lines during power-up if voltages on word lines in the array during power-up cause access transistors for the SRAM cells to become conductive.

Claims

1. A computer system, comprising:

a processor having a processor bus;

at least one input device coupled to the processor through the processor bus;

at least one output device coupled to the processor through the processor bus;

at least one data storage devices coupled to the processor through the processor bus;

a system memory coupled to the processor through the processor bus; and

a static random access cache memory coupled to the processor through the processor bus, the static random access cache memory comprising;

an address bus;

a control bus;

a data bus;

an address decoder coupled to the address bus;

a read/write circuit coupled to the data bus;

a memory-cell array coupled to the address decoder, control circuit, and read/write circuit;

the memory-cell array comprising;

an array of SRAM cells arranged in rows and columns, each of the SRAM cells including a pair of access switches each having an access terminal and a control terminal;

a wordline coupled to the control terminal of each of the access switches in a respective row;

a pair of complementary digit lines coupled to respective access terminals of each of the access switches in a respective column;

a respective sense amplifier coupled between the complementary digit lines in each of the pairs of complementary digit lines;

a respective write driver coupled between the complementary digit lines in each of the pairs of complementary digit lines; and

a respective equilibration switch coupled between the complementary digit lines in each of the pairs of complementary digit lines;

a bias circuit coupled to each of the digit lines, the bias circuit being operable to couple a bias current to the digit lines in a normal mode and to couple a voltage to the digit lines that maintains the access switches non-conductive in a power-up mode; and

a control circuit operable to control the operation of the SRAM.

2. The computer system of claim 1 wherein the bias circuit comprises:

a respective bias transistor coupled between a supply node and each of the digit lines;

a bias supply transistor coupled between a supply voltage and the supply node of each bias transistor; and

a power-up circuit coupled to a gate of the bias transistor, the power-up circuit being operable in a normal mode to couple a voltage to the gate of the bias supply transistor that renders the bias supply transistor conductive, and being operable in the power-up mode to couple a voltage to the gate of the bias supply transistor that renders the bias supply transistor non-conductive.

3. The computer system of claim 2 wherein the bias supply transistor comprises a PMOS transistor coupled to a positive supply voltage, wherein each of the access switches comprise PMOS access transistors, wherein each of the SRAM cells comprise a loadless 4-T SRAM cell, wherein each of the bias transistors comprise a PMOS transistor, and wherein the power-up circuit is operable to couple substantially ground potential to the gate of the PMOS bias supply transistor in the normal mode and to couple the gate of the PMOS bias supply transistor to substantially the positive supply voltage in the power-up mode.

4. The computer system of claim 1 wherein the bias circuit comprises:

a respective bias transistor coupled between a supply terminal and each of the digit lines; and

a power-up circuit coupled to the supply terminal of each of the bias transistors, the power-up circuit being operable in a normal mode to couple a supply voltage from the positive supply voltage to the supply terminal of each of the bias transistors, and being operable in the power-up mode isolate the power supply voltage from the supply terminal of each of the bias transistors.

5. The computer system of claim 4 wherein each of the SRAM cells comprise a loadless 4-T SRAM cell having PMOS access transistors, and wherein each of the bias transistors comprise a PMOS transistor.

6. The computer system of claim 1 wherein the bias circuit comprises:

a respective bias transistor coupled between a supply voltage and each of the digit lines; and

a power-up circuit coupled to a gate of each of the bias transistors, the power-up circuit receiving a power-up signals and a digit line load signal corresponding to the bias transistors for each pair of complementary digit lines, the power-up circuit being operable in response to a power-up signal indicative of a normal mode to couple each of the digit line load signals to the gate of the respective bias transistor to renders the bias transistors conductive, and being operable in response to a power-up signal indicative of a power-up mode to couple a voltage to the gate of the bias transistors that renders the bias transistors non-conductive.

7. The computer system of claim 6 wherein each of the SRAM cells comprise a loadless 4-T SRAM cell having PMOS access transistors, and wherein each of the bias transistors comprise a PMOS transistor.

8. The computer system of claim 1 wherein the bias circuit comprises:

a respective bias transistor coupled between a supply voltage and each of the digit lines; and

a power-up circuit coupled to a gate of each of the bias transistors, the power-up circuit being operable in a normal mode to apply a voltage to a gate of each of the bias transistors that renders the bias transistors conductive, and being operable in a power-up mode to apply a voltage to the gate of each of the bias transistors that renders the bias transistors non-conductive.

9. The computer system of claim 8 wherein each of the SRAM cells comprise a loadless 4-T SRAM cell having PMOS access transistors, and wherein each of the bias transistors comprise a PMOS transistor.

10. The computer system of claim 1 wherein each of the access switches comprise PMOS access transistors, wherein each of the SRAM cells comprise a loadless 4-T SRAM cell, and wherein the bias circuit is operable to couple a positive current to the digit lines in the normal mode and to terminate coupling the positive current from the digit lines in the power-up mode.

11. The computer system of claim 1 wherein each of the access switches comprise a transistor, the access terminal for each of the access switches comprises a drain or a source of the access transistor, and the control terminal for each of the access switches comprises a gate of the access transistor.

12. The computer system of claim 1, wherein the SRAM comprises a synchronous SRAM.