Integrated circuit having redundant, self-organized architecture for improving yield

• US 6,717,869 B2
• Filed: 04/25/2002
• Issued: 04/06/2004
• Est. Priority Date: 04/25/2002
• Status: Expired due to Fees

• Current Assignee: DSP Group Ltd. (Synaptics Incorporated)
• Original Assignee: DSP Group Ltd. (Synaptics Incorporated)
• Inventors: Koretsky, Victor
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US10/134,090
• Publication Number:
  US 20030202388A1
• Time in Patent Office: 712 Days
• Field of Search: 365/200, 365/226, 365/201
• US Class Current: 365/200
• CPC Class Codes: G06F 11/27 Built-in tests

Abstract

An integrated circuit architecture having a common circuit including a system controller and a data bus coupled to a plurality of redundant processing units, or clusters, each adapted to perform self-diagnosis and to report a status thereof to the system controller via a status line. The system controller is adapted to disconnect a faulty or unresponsive cluster from the common circuit in order to allow normal operation of remaining operative components. By such means yield of the integrated circuit is increased as well as the reliability of a device containing the integrated circuit.

Claims

1. A method for increasing the yield and/or reliability of an integrated circuit having a common circuit, said method comprising:

(a) connecting to the common circuit a plurality of mutually redundant clusters each having a respective processing unit and associated auxiliary components,

(b) self-testing the respective processing unit in each cluster, and

(c) disconnecting a faulty or unresponsive cluster from the common circuit so that failure of one cluster does not cause failure of the integrated circuit.

2. The method according to claim 1, wherein steps (b) and (c) include:

i) successively self-testing each cluster and reporting a status thereof to a system controller, and

ii) the system controller disconnecting a faulty or unresponsive cluster from the common circuit.

3. The method according to claim 1, wherein steps (b) and (c) include:

i) successively self-testing each cluster and reporting a status thereof to a system controller,

ii) the system controller disconnecting a faulty and unresponsive cluster from the common circuit, and

iii) a faulty and responsive cluster self-disconnecting from the common circuit.

4. The method according to claim 2, wherein the system controller is responsive to initiation of power on for controlling each of the clusters successively to perform said self-diagnosis.

5. The method according to claim 3, wherein the system controller is responsive to initiation of power on for controlling each of the clusters successively to perform said self-diagnosis.

6. The method according to claim 2, wherein an active cluster is adapted to self-test during operation of a device containing said integrated circuit and to self-disconnect upon failure and a redundant cluster is either substituted therefor or tasks are re-distributed among remaining operational clusters.

7. The method according to claim 3, wherein an active cluster is adapted to self-test during operation of a device containing said integrated circuit and to self-disconnect upon failure and a redundant cluster is either substituted therefor or tasks are re-distributed among remaining operational clusters.

8. An integrated circuit architecture comprising:

a common circuit including a system controller and a data bus coupled to a plurality of redundant processing units, or clusters, each adapted to perform self-diagnosis and to report a status thereof to the system controller via a status line;

said system controller being adapted to disconnect a faulty or unresponsive cluster from the common circuit in order to allow normal operation of remaining operative components.

9. The integrated circuit architecture according to claim 8, wherein the system controller is responsive to initiation of power on for controlling each of the clusters successively to perform said self-diagnosis.

10. The integrated circuit architecture according to claim 8, wherein the status line is a common status line serving each of the clusters.

11. The integrated circuit architecture according to claim 8, wherein each cluster is provided with a respective status line.

12. The integrated circuit architecture according to claim 8, wherein the data bus includes a common data bus switchably coupled to a plurality data buses to each of which a respective one of the clusters is connected, thereby allowing the data bus in respect of a faulty cluster to be disconnected from the common data bus.

13. The integrated circuit architecture according to claim 8, wherein a faulty and responsive cluster is adapted to self-disconnect and report to the system controller.

14. An integrated circuit architecture comprising:

a common circuit including a common data bus switchably coupled to a plurality of redundant processing units, or clusters, each via a respective data bus and each cluster and its associated data bus adapted for disconnection from the common circuit if found to be faulty and to provide a fault status thereof to the common circuit via a status line;

wherein the common circuit is responsive to initiation of power on for controlling each of the clusters successively to perform self-diagnosis.

15. An integrated circuit architecture comprising:

a common circuit including a common data bus switchably coupled to a plurality of redundant processing units, or clusters, each via a respective data bus and each cluster and its associated data bus adapted for disconnection from the common circuit if found to be faulty and to provide a fault status thereof to the common circuit via a common status line serving each of the clusters.

16. An integrated circuit architecture comprising:

a common circuit including a common data bus switchably coupled to a plurality of redundant processing units, or clusters, each via a respective data bus and each cluster and its associated data bus adapted for disconnection from the common circuit if found to be faulty and to provide a fault status thereof to the common circuit via a respective status line coupled to the common circuit.

17. An integrated circuit architecture comprising:

a common circuit including a common data bus switchably coupled to a plurality of redundant processing units, or clusters, each via a respective data bus and each cluster and its associated data bus adapted for disconnection from the common circuit if found to be faulty and to provide a fault status thereof to the common circuit;

wherein a faulty and responsive cluster is adapted to self-disconnect and report to the common circuit.

18. An integrated circuit architecture comprising:

a common circuit including a common data bus switchably coupled to a plurality of redundant processing units, or clusters, each via a respective data bus and each cluster and its associated data bus adapted for disconnection from the common circuit if found to be faulty and to provide a fault status thereof to the common circuit;

wherein the common circuit is adapted to disconnect a faulty and unresponsive cluster a predetermined time interval after requesting a self-test.

19. An integrated circuit architecture comprising:

a common circuit including a common data bus switchably coupled to a plurality of redundant processing units, or clusters, each via a respective data bus and each cluster and its associated data bus adapted for disconnection from the common circuit if found to be faulty and to provide a fault status thereof to the common circuit;

wherein the clusters are adapted to self-test during operation of a device containing said integrated circuit and to self-disconnect a cluster from the common circuit upon failure thereof.