System and method for synchronized control of system simulators with multiple processor cores

• US 6,718,294 B1
• Filed: 05/16/2000
• Issued: 04/06/2004
• Est. Priority Date: 05/16/2000
• Status: Expired due to Term

• Current Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Original Assignee: Mindspeed Technologies Inc. (MACOM Technology Solutions Holdings, Inc.)
• Inventors: Bortfeld, Ulrich
• Primary Examiner(s): Broda, Samuel
• Application Number:
  US09/571,924
• Time in Patent Office: 1,421 Days
• Field of Search: 703/14-28, 709/102, 717/134, 717/135, 714/37, 714/45-46
• US Class Current: 703/20
• CPC Class Codes: G06F 11/3632 of specific synchronisation aspects
• CPC Class Codes: G06F 11/3664 Environments for testing or debugging software

Abstract

A debugging environment for a multi-processor simulator or emulator is disclosed. The simulator or emulator is ideally suited for the development of embedded software. The simulator can contain multiple processor models, with each processor model representing a processor. The simulator or emulator also includes a scheduler which controls the execution of the processor models. Each processor also communicates with a debugger via a debug adapter. The debug adapter acts as a pass-through filter for non-control commands which are communicated between a processor and its attached debugger. However, the debug adapter routes control commands to the scheduler. The scheduler ensures that all of the processors and debuggers maintain synchronization. Other modules can also be included in the multi-processor simulation environment, for example, clock gate modules.

Claims

1. A system for maintaining synchronization while debugging a multi-processor system, said system comprising:

a. a scheduler;

b. a plurality of processors which communicate with said scheduler;

c. a plurality of debug adapters, wherein each of said processors communicates with at least one of said debug adapters, and wherein each of said debug adapters communicates with said scheduler; and

d. a plurality of debuggers, wherein each of said debug adapters communicates with at least one of said debuggers;

wherein said scheduler, said plurality of processors, said plurality of debug adapters, and said plurality of debuggers are implemented in software.

2. The system of claim 1, wherein a plurality of control commands are communicated between said debug adapters and said scheduler.

3. The system of claim 1, wherein said system is implemented using a simulator.

4. The system of claim 1, wherein said system is implemented using an emulator.

5. The system of claim 1, further comprising a plurality of clock gate modules, wherein said clock gate modules allow said processors to be selectively halted.

6. The system of claim 1, wherein the communications between said processors and said scheduler comprise API calls.

7. The system of claim 1, wherein the communications between said debug adapters and said scheduler comprise API calls.

8. The system of claim 1, wherein a plurality of processes are running on at least one of said processors.

9. A method for maintaining synchronization while debugging a multi-processor system, comprising:

a. running at least one software application on at least one processor;

b. running the at least one software application in a debug mode using a debugger, wherein the at least one processor and the debugger communicate via a debug adapter; and

c. transmitting at least one control command from the debug adapter to a scheduler;

wherein said at least one processor, said debugger, said debug adapter, and said scheduler are implemented in software.

10. The method of claim 9, further comprising the step of transmitting at least one non-control command between the at least one processor and the debugger via the debug adapter.

11. The method of claim 9, wherein running the at least one software application is accomplished using a plurality of step functions.

12. The method of claim 11, wherein each step in the plurality of step functions is measured using a master clock cycle.

13. The method of claim 11, wherein each step in the plurality of step functions is performed on all of the software applications and the step function for each of the software applications comprises:

a. an update function; and

b. a recalc function.

14. The method of claim 11, wherein the at least one software application executes in a run mode by continuously executing a plurality of the step functions.

15. The method of claim 9, further comprising selectively halting processors using at least one clock gate module.

16. In a computer simulation system having a scheduler, a plurality of processor models, a plurality of debuggers and a plurality of debug adapters, a computer-readable medium holding computer executable instructions for performing a method comprising the steps of:

a. running at least one software application on at least one processor;

b. running the at least one software application in a debug mode using at least one debugger;

c. transmitting a plurality of non-control commands between the at least one processor and the at least one debugger via at least one debug adapter; and

d. transmitting a plurality of control commands from the at least one debug adapter to a schedulers;

wherein said at least one processor, said at least one debugger, said at least one debug adapter, and said scheduler are implemented in software.

17. The computer simulation system of claim 16, wherein the computer executable instructions further comprise the step of transmitting at least one non-control command between the at least one processor and the debugger via the debug adapter.