Multiplexer selecting one of input/output data from a low pin count interface and a program information to update a firmware device from a communication interface

• US 6,718,407 B2
• Filed: 09/30/1999
• Issued: 04/06/2004
• Est. Priority Date: 09/30/1999
• Status: Expired due to Term

• Current Assignee: Beijing Xiaomi Mobile Software Co., Ltd. (Xiaomi Corp.)
• Original Assignee: Intel Corporation
• Inventors: Martwick, Andrew W.
• Primary Examiner(s): Park, Ilwoo
• Application Number:
  US09/410,133
• Publication Number:
  US 20030041182A1
• Time in Patent Office: 1,650 Days
• Field of Search: 717/168-173, 710/36, 710/51, 709/217-219, 713/1, 713/2, 713/100, 711/103
• US Class Current: 710/51
• CPC Class Codes: G06F 8/65 Updates security arrangements therefor G06F21/57

Abstract

The present invention is a method and apparatus to self update a firmware device. A communication interface receives programming information. A parser coupled to the communication interface to parse the programming information into control commands and program data.

Claims

1. A method comprising:

receiving programming information to update a firmware device containing a boot code in a chipset from a communication interface;

parsing the programming information into control commands and program data by a parser;

programming the firmware device based on the control commands by a control logic circuit;

storing the program data to be written into the firmware device in a buffer; and

providing the programming information to the parser by a source selector, comprising;

selecting one of the programming information from the communication interface and an input and output (I/O) data channel by a multiplexer, the I/O data channel being a low pin count (LPC) interface, and

controlling a selection of the multiplexer by a multiplexer controller.

2. The method of claim 1 wherein programming the firmware device comprises:

erasing the firmware device by an erase control circuit; and

writing to the firmware device using the program data in the buffer by a write control circuit.

3. The method of claim 1 wherein the parsing comprises:

generating the control commands based on the parsed programming information by a state machine, the control commands including at least an erase command and a write command.

4. The method of claim 3 wherein the programming information includes at least a self-update identifier, program parameters, and the program data.

5. The method of claim 4 wherein generating the control commands comprises:

recognizing the self-update identifier;

reading the program parameters including at least erase and write addresses;

generating a buffer write command to write the program data into the buffer;

generating an erase command to the erase control circuit to a block in the firmware device at the erase address; and

generating a write command to the write control circuit to the program data in the buffer to the firmware device at the write address.

6. The method of claim 1 wherein receiving comprises:

converting serial data into the programming information by a serial to parallel converter.

7. An apparatus comprising:

a communication interface to receive programming information to update a firmware device containing a boot code in a chipset;

a parser coupled to the communication interface to parse the programming information into control commands and program data;

a control logic circuit coupled to the parser to program the firmware device based on the control commands;

a buffer coupled to the parser to store the program data to be written into the firmware device; and

a source selector coupled to the communication interface and the parser to provide the programming information to the parser, comprising;

a multiplexer to select one of the programming information from the communication interface and an input and output (I/O) data channel, the I/O data channel being a low pin count (LPC) interface, and

a multiplexer controller coupled to the multiplexer to control a selection of the multiplexer.

8. The apparatus of claim 7 wherein the control logic circuit comprises:

an erase control circuit to erase the firmware device; and

a write control circuit to write the firmware device using the program data in the buffer.

9. The apparatus of claim 7 wherein the parser comprises:

a state machine to generate the control commands based on the parsed programming information, the control commands including at least an erase command and a write command.

10. The apparatus of claim 9 wherein the programming information includes at least a self-update identifier, program parameters, and program data.

11. The apparatus of claim 10 wherein the state machine comprises:

a self-update identification state to recognize the self-update identifier;

a program parameters read state coupled to the self-update identification state to read the program parameters including at least erase and write addresses;

a program data buffer state to generate a buffer write command to write the program data into the buffer;

a block erasure state to generate the erase command, the erase command causing the erase control circuit to erase a block in the firmware device at the erase address; and

a block write state to generate the write command, the write command causing the write control circuit to write the program data in the buffer to the firmware device at the write address.

12. The apparatus of claim 7 wherein the communication interface includes a serial to parallel converter to convert serial data into the programming information.

13. A system comprising:

a host processor;

a firmware device containing a boot code in a chipset; and

a self-update firmware controller coupled to the firmware device to self update the firmware device, the controller comprising;

a communication interface to receive programming information,

a parser coupled to the communication interface to parse the programming information into control commands and program data,

a control logic circuit coupled to the parser to program the firmware device based on the control commands,

a buffer coupled to the parser to store the program data to be written into the firmware device, and

a source selector coupled to the communication interface and the parser to provide the programming information to the parser, comprising;

a multiplexer to select one of the programming information from the communication interface and an input and output (I/O) data channel, the I/O data channel being a low pin count (LPC) interface, and

a multiplexer controller coupled to the multiplexer to control a selection of the multiplexer.

14. The system of claim 13 wherein the control logic circuit comprises:

an erase control circuit to erase the firmware device; and

a write control circuit to write the firmware device using the program data in the buffer.

15. The system of claim 13 wherein the parser comprises:

a state machine to generate the control commands based on the parsed programming information, the control commands including at least an erase command and a write command.

16. The system of claim 15 wherein the programming information includes at least a self-update identifier, program parameters, and program data.

17. The system of claim 16 wherein the state machine comprises:

a self-update identification state to recognize the self-update identifier;

a program parameters read state coupled to the self-update identification state to read the program parameters including at least erase and write addresses;

a program data buffer state to generate a buffer write command to write the program data into the buffer;

a block erasure state to generate the erase command, the erase command causing the erase control circuit to erase a block in the firmware device at the erase address; and

a block write state to generate the write command, the write command causing the write control circuit to write the program data in the buffer to the firmware device at the write address.

18. The system of claim 13 wherein the communication interface includes a serial to parallel converter to convert serial data into the programming information.