Low-K gate spacers by fluorine implantation

• US 6,720,213 B1
• Filed: 01/15/2003
• Issued: 04/13/2004
• Est. Priority Date: 01/15/2003
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Mandelman, Jack, Gambino, Jeffrey P., Tonti, William R.
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): PHAM, HOAI V
• Application Number:
  US10/345,344
• Time in Patent Office: 454 Days
• Field of Search: 438/184, 438/185, 438/199, 438/230, 438/265, 438/303, 438/595
• US Class Current: 438/184
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/31155 by ion implantation
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

A MOSFET device and a method of fabricating a MOSFET device having low-K dielectric oxide gate sidewall spacers produced by fluorine implantation. The present invention implants fluorine into the gate oxide sidewall spacers which is used to alter the properties of advanced composite gate dielectrics e.g. nitridized oxides, NO, and gate sidewall dielectrics, such that the low-K properties of fluorine are used to develop low parasitic capacitance MOSFETs.

Claims

1. A method of fabricating a MOSFET device having low-K dielectric oxide gate sidewall spacers formed by fluorine implantation, such that the implanted fluorine alters the properties of the gate sidewall spacers to develop a low parasitic capacitance MOSFET, comprising:

fabricating a MOSFET device structure;

forming a silicon nitride etch stop layer over the fabricated MOSFET device structure of the previous step;

depositing an oxide layer over the silicon nitride etch stop layer on the surfaces of the fabricated structure of the previous step to protect the substrate from a subsequent fluorine implant;

performing a fluorine implant through the silicon nitride etch stop layer and into the oxide gate sidewall spacers to form low-K fluorine doped oxide gate sidewall spacers.

2. The method of claim 1, wherein the step of performing a fluorine implant is performed with an implant dosage and implant energy to lower the dielectric constant of the MOSFET device from a value of substantially 4.0 to a value in the range of 3.3 to just below 4.0.

3. The method of claim 1, wherein the step of performing a fluorine implant is performed with an implant dosage and implant energy to achieve a dielectric constant for the MOSFET device of substantially 3.3.

4. The method of claim 1, further including stripping the oxide layer selective to the silicon nitride etch stop layer, and then oxidizing the silicon nitride layer to convert the silicon nitride etch stop to an oxide.

5. The method of claim 4, wherein the step of oxidizing the silicon nitride layer is performed with an ISSG oxidation process.

6. The method of claim 1, wherein the step of depositing includes depositing the oxide layer primarily on horizontal surfaces of the fabricated structure.

7. The method of claim 1, wherein the step of fabricating includes fabricating the MOSFET device on a silicon substrate by forming the shallow trench isolation STI, implanting the wells, forming the gate dielectric, and depositing and patterning the gate stack, implanting the source/drain extensions and forming the oxide gate sidewall spacers.

8. The method of claim 1, wherein the step of performing a fluorine implant comprises performing an angled, at an angle of 10 to 90 degrees relative to an upper horizontal surface of a wafer containing the MOSFET device, fluorine implant through the silicon nitride etch stop layer and into the oxide gate sidewall spacers to form the low-K fluorine doped oxide gate sidewall spacers.

9. The method of claim 1, wherein the step of performing a fluorine implant comprises performing an angled, at an angle of substantially 45 degrees relative to an upper horizontal surface of a wafer containing the MOSFET device, fluorine implant through the silicon nitride etch stop layer and into the oxide gate sidewall spacers to form the low-K fluorine doped oxide gate sidewall spacers.

10. The method of claim 1, wherein the silicon nitride layer is deposited by chemical vapor deposition.

11. The method of claim 1, wherein the fluorine implant penetrates the oxide gate sidewall spacers and not the gate dielectric.

12. The method of claim 1, wherein the fluorine implant influences a junction/contact region of the MOSFET device to locally alter the gate dielectric characteristic, increasing the threshold voltage of the device.

13. The method of claim 1, wherein the step of performing a fluorine implant comprises performing an angled fluorine implant through the silicon nitride etch stop layer and into the oxide gate sidewall spacers to form the low-K fluorine doped oxide gate sidewall spacers.

14. The method of claim 13, wherein the fluorine implant penetrates the oxide gate sidewall spacers and not the gate dielectric.

15. The method of claim 13, wherein the fluorine implant influences a junction/contact region of the MOSFET device to locally alter the gate dielectric characteristic, increasing the threshold voltage of the device.