Method of fabricating semiconductor device

• US 6,720,220 B2
• Filed: 12/23/2002
• Issued: 04/13/2004
• Est. Priority Date: 08/28/1997
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi ULSI Systems Company Limited (Hitachi, Ltd.), Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Imai, Yasuo, Oishi, Kentaro, Kudo, Satoshi, Nakazawa, Yoshito, Shigematsu, Takashi, Uesawa, Kozo, Kobayashi, Masayoshi, Ohnishi, Akihiro, Numazawa, Sumito, Kubo, Sakae
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): KESHAVAN, BELUR V
• Application Number:
  US10/325,915
• Publication Number:
  US 20030124806A1
• Time in Patent Office: 477 Days
• Field of Search: 438/270, 438/212, 438/268, 438/329, 438/328, 438/332, 438/342, 438/259, 438/272, 257/330, 257/327, 257/342, 257/328, 257/374, 257/397, 257/622, 257/170, 257/334, 257/129, 257/341
• US Class Current: 438/270
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

Claims

1. A method of fabricating a semiconductor device having a gate lead-out region and a MISFET-forming region, comprising the steps of:

forming a trench in said MISFET-forming region in a semiconductor substrate;

forming a gate oxide film of said MISFET in said trench;

forming a gate electrode of said MISFET over said gate oxide film; and

forming a first conductive film over said semiconductor substrate in said gate lead-out region;

wherein the top surface of said gate electrode is lower than the top surface of said semiconductor substrate in said gate lead-out region, and

wherein said gate electrode is electrically connected with said first conductive film.

2. A method of fabricating a semiconductor device according to claim 1, wherein said gate electrode and first conductive film include polycrystalline silicon.

3. A method of fabricating a semiconductor device according to claim 1, further comprising the steps of:

forming a first insulation film over said first conductive film; and

forming a second conductive film over said first insulation film;

wherein said first and second conductive films are electrically connected together.

4. A method of fabricating a semiconductor device having a gate lead-out region and a MISFET-forming region, comprising the steps of:

forming a plurality of trenches in said MISFET-forming region in a semiconductor substrate;

forming gate oxide films of said MISFETs in said trenches;

forming gate electrodes of said MISFETs over said gate oxide films; and

forming a first conductive film over said semiconductor substrate in said gate lead-out region;

wherein the top surface of said gate electrodes is lower than the top surface of said semiconductor substrate in said gate lead-out region;

wherein said plurality of gate electrodes are electrically connected with said first conductive film; and

wherein said plurality of gate electrodes are disposed in parallel with each other.

5. A method of fabricating a semiconductor device according to claim 4, wherein said plurality of gate electrodes are electrically connected together.