Structure and method for dual gate oxide thicknesses

• US 6,720,221 B1
• Filed: 08/30/2001
• Issued: 04/13/2004
• Est. Priority Date: 02/28/2000
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Primary Examiner(s): Dang, Phuc T.
• Application Number:
  US09/943,398
• Time in Patent Office: 957 Days
• Field of Search: 438/258, 438/261, 438/275, 438/283, 438/287, 438/433, 438/440, 438/449, 438/528, 438/981
• US Class Current: 438/275
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

Abstract

Structures and methods involving at least a pair of gate oxides having different thicknesses, one suitable for use in a logic device and one suitable for use in a memory device, have been shown. The method provided by the present invention affords a technique for ultra thin dual gate oxides having different thicknesses using a low temperature process in which no etching steps are required. The method includes forming a pair of gate oxides to a first thickness, which in one embodiment, includes a thickness of less than 5 nanometers. In one embodiment, forming the pair of gate oxides includes using a low-temperature oxidation method. A thin dielectric layer is then formed on one of the pair of gate oxides which is to remain as a thin gate oxide region for a transistor for use in a logic device. The thin dielectric layer exhibits a high resistance to oxidation at high temperatures. In one embodiment, the thin dielectric layer includes a thin dielectric layer of silicon nitride (Si₃N₄) formed using jet vapor deposition (JVD). The other of the pair of gate oxides is then formed to a second thickness to serve as a thick gate oxide region for a transistor for use in a memory device. Another embodiment of the present invention includes the structure of a logic device and a memory device formed on a single substrate as well as systems formed according to the method described above. In one embodiment, a dielectric layer of the transistor for use in the logic device has a thickness of less than 7 nanometers and a dielectric layer in the transistor for use in the memory device has a thickness of less than 12 nanometers.

Claims

1. A method for forming gate oxides on a substrate, comprising:

forming a pair of gate oxides to a first thickness on the substrate;

forming a dielectric layer on one of the pair of gate oxides, wherein the dielectric layer exhibits a higher resistance to oxidation than the gate oxides; and

forming the other of the pair of gate oxides to a second thickness different from the first thickness.

2. The method of claim 1, wherein forming the pair of gate oxides to a first thickness includes forming the pair of gate oxides to a thickness of less than 5 nanometers.

3. The method of claim 1, wherein forming the pair of gate oxides to a first thickness includes forming the pair of gate oxides at a temperature of less than or equal to approximately 400 degrees Celsius.

4. The method of claim 1, wherein forming the pair of gate oxides to a first thickness includes forming the pair of gate oxides by atomic oxygen generated in a krypton plasma process.

5. The method of claim 1, wherein forming a dielectric layer on one of the pair of gate oxides includes forming a dielectric layer of less than 5 nanometers of silicon nitride (Si3N4) using jet vapor deposition (JVD).

6. A method for forming gate oxides on a substrate, comprising:

forming a pair of gate oxides to a first thickness on the substrate;

forming a dielectric layer on one of the pair of gate oxides, wherein the dielectric layer exhibits a higher resistance to boron penetration than the gate oxides; and

forming the other of the pair of gate oxides to a second thickness different from the first thickness.

7. The method of claim 6, wherein forming the pair of gate oxides to a first thickness includes forming the pair of gate oxides to a thickness of less than 5 nanometers by atomic oxygen generated in a krypton plasma process.

8. The method of claim 6, wherein forming a dielectric layer on one of the pair of gate oxides includes forming a dielectric layer of silicon nitride (Si3N4) to a thickness of less than 3 nanometers using jet vapor deposition (JVD).

9. The method of claim 6, wherein forming a dielectric layer on one of the pair of gate oxides includes forming a dielectric layer which resists formation of an interfacial oxide layer when forming the other of the pair of gate oxides to a second thickness.

10. The method of claim 6, wherein forming the other of the pair of gate oxides to a second thickness includes forming the other of the pair of gate oxides to a second thickness of less than 10 nanometers by atomic oxygen generated in a krypton plasma process.

11. A method for forming gate oxides on a substrate, comprising:

forming a pair of gate oxides to a first thickness on the substrate;

forming a masking layer on one of the pair of gate oxides having a first thickness, wherein the masking layer exhibits a higher resistance to oxidation than the gate oxides; and

forming the other of the pair of gate oxides to a second thickness different from the first thickness.

12. The method of claim 11, wherein forming the pair of gate oxides to a first thickness includes forming the pair of gate oxides to a thickness of less than 5 nanometers.

13. The method of claim 11, wherein forming the pair of gate oxides includes forming the pair of gate oxides by atomic oxygen generated in a krypton plasma process.

14. The method of claim 11, wherein forming the other of the pair of gate oxides to a second thickness includes forming the other of the pair of gate oxides to a second thickness of less than 10 nanometers by atomic oxygen generated in a krypton plasma process.

15. The method of claim 11, wherein forming a masking layer on one of the pair of gate oxides, includes forming a masking layer of silicon nitride (Si3N4) to a thickness of less than 3 nanometers using jet vapor deposition (JVD).

16. A method for forming gate oxides on a substrate, comprising:

forming a pair of gate oxides to a first thickness on the substrate, wherein forming the pair of gate oxides to a first thickness includes forming the pair of gate oxides to a thickness of less than 5 nanometers (nm) by plasma generated atomic oxygen;

forming a dielectric layer on one of the pair of gate oxides, wherein the dielectric layer exhibits a higher resistance to oxidation than the gate oxides; and

forming the other of the pair of gate oxides to a second thickness different from the first thickness.

17. The method of claim 16, wherein forming a dielectric layer on one of the pair of gate oxides includes forming a dielectric layer of silicon nitride (Si3N4) using jet vapor deposition (JVD).

18. The method of claim 16, wherein forming a dielectric layer on one of the pair of gate oxides includes forming a dielectric layer which exhibits higher resistance to boron penetration than the gate oxides.

19. The method of claim 16, wherein forming a pair of gate oxides to a first thickness on the substrate includes forming a pair of gate oxides to a first thickness on the substrate by krypton plasma generated atomic oxygen.

20. The method of claim 16, wherein forming a pair of gate oxides to a first thickness on the substrate includes forming a pair of gate oxides to a first thickness on the substrate at a temperature of less than or equal to approximately 400 degrees Celsius.

21. A method for forming gate oxides on a substrate, comprising:

forming a pair of gate oxides to a first thickness on the substrate, wherein forming the pair of gate oxides to a first thickness includes forming the pair of gate oxides to a thickness of less than 5 nanometers (nm) by plasma generated atomic oxygen;

forming a dielectric layer on one of the pair of gate oxides, wherein the dielectric layer exhibits a higher resistance to boron penetration than the gate oxides; and

forming the other of the pair of gate oxides to a second thickness different from the first thickness.

22. The method of claim 21, wherein forming a dielectric layer on one of the pair of gate oxides includes forming a dielectric layer of silicon nitride (Si3N4) using jet vapor deposition (JVD).

23. The method of claim 21, wherein forming a dielectric layer on one of the pair of gate oxides includes forming a dielectric layer which exhibits higher resistance to oxidation than the gate oxides.

24. The method of claim 21, wherein forming a pair of gate oxides to a first thickness on the substrate includes forming a pair of gate oxides to a first thickness on the substrate by krypton plasma generated atomic oxygen.

25. The method of claim 21, wherein forming a pair of gate oxides to a first thickness on the substrate includes forming a pair of gate oxides to a first thickness on the substrate at a temperature of less than or equal to approximately 400 degrees Celsius.

26. A method for forming gate oxides on a substrate, comprising:

forming a pair of gate oxides to a first thickness on the substrate, wherein forming the pair of gate oxides to a first thickness includes forming the pair of gate oxides to a thickness of less than 5 nanometers (nm) by plasma generated atomic oxygen;

forming a layer of silicon nitride (Si3N4) on one of the pair of gate oxides using jet vapor deposition (JVD); and

forming the other of the pair of gate oxides to a second thickness different from the first thickness.

27. The method of claim 26, wherein forming a layer of silicon nitride on one of the pair of gate oxides includes forming a layer of silicon nitride to a thickness of less than 3 nanometers.

28. The method of claim 26, wherein forming a pair of gate oxides to a first thickness on the substrate includes forming a pair of gate oxides to a first thickness on the substrate by krypton plasma generated atomic oxygen.

29. The method of claim 26, wherein forming a pair of gate oxides to a first thickness on the substrate includes forming a pair of gate oxides to a first thickness on the substrate at a temperature of less than or equal to approximately 400 degrees Celsius.

30. A method for forming gate oxides on a substrate, comprising:

forming a pair of gate oxides to a first thickness on the substrate, wherein forming the pair of gate oxides to a first thickness includes forming the pair of gate oxides to a thickness of less than 5 nanometers (nm) by krypton plasma generated atomic oxygen at less than or equal to approximately 400 degrees Celsius;

forming a dielectric layer on one of the pair of gate oxides, wherein the dielectric layer exhibits higher resistance to oxidation than the gate oxides; and

forming the other of the pair of gate oxides to a second thickness different from the first thickness.

31. The method of claim 30, wherein forming the other of the pair of gate oxides to a second thickness includes forming the other of the pair of gate oxides to a second combined thickness of less than 12 nanometers (nm).

32. The method of claim 30, wherein forming a dielectric layer on one of the pair of gate oxides includes forming a dielectric layer on one of the pair of gate oxides to a combined thickness of less than 7 nanometers (nm).

33. The method of claim 30, wherein forming a dielectric layer on one of the pair of gate oxides includes forming a dielectric layer which is approximately a third of the first thickness of the gate oxide.