Integrated circuit inductor structure and non-destructive etch depth measurement
First Claim
1. In the fabrication of an integrated circuit, particularly an integrated circuit for radio frequency applications, a method for forming an electrical device structure comprised in said circuit, the method comprising:
- providing a semiconductor substrate;
forming a first dielectric layer above said substrate;
forming a plurality of through holes in said first dielectric layer;
removing semiconductor substrate material under the first dielectric layer by means of isotropic etching using said first dielectric layer provided with through holes as hardmask, thus forming at least a first cavity in the semiconductor substrate underneath said plurality of through holes;
forming a second dielectric layer on top of said first dielectric layer to plug said plurality of through holes, thereby creating a membrane above said first cavity; and
creating an electrical device above said membrane.
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Accused Products
Abstract
A method for forming an electrical device structure in an integrated circuit comprises providing a substrate; forming a passivation layer thereon; forming a plurality of through holes in the passivation layer, the through holes; removing substrate material under the passivation layer by means of isotropic etching, thus forming at least a first cavity in the substrate beneath the plurality of through holes; forming a dielectric layer on top of the passivation layer to plug the through holes, thereby creating a membrane; and creating an electrical device, such as e.g. an inductor, above the membrane.
41 Citations
23 Claims
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1. In the fabrication of an integrated circuit, particularly an integrated circuit for radio frequency applications, a method for forming an electrical device structure comprised in said circuit, the method comprising:
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providing a semiconductor substrate;
forming a first dielectric layer above said substrate;
forming a plurality of through holes in said first dielectric layer;
removing semiconductor substrate material under the first dielectric layer by means of isotropic etching using said first dielectric layer provided with through holes as hardmask, thus forming at least a first cavity in the semiconductor substrate underneath said plurality of through holes;
forming a second dielectric layer on top of said first dielectric layer to plug said plurality of through holes, thereby creating a membrane above said first cavity; and
creating an electrical device above said membrane. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
said through holes are dividable into a first and a second sub-group, respectively, wherein adjacent through holes within a sub-group are more closely located than adjacent through holes belonging to different sub-groups;
semiconductor substrate material is removed under the first dielectric layer to form a second cavity in the semiconductor substrate underneath said plurality of through holes, said first and second cavities being separated by a portion of semiconductor substrate material; and
said second dielectric layer formed on top of said first dielectric layer to plug said plurality of through holes is supported at least by said portion of semiconductor substrate material.
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17. The method as claimed in claim 16 wherein the distance between adjacent through holes belonging to different sub-groups of through holes is large enough to ensure that said portion of semiconductor substrate separating the cavities formed beneath said different sub-groups is capable of supporting said membrane mechanically and hindering the same from collapsing.
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18. The method as claimed in claim 17 wherein the distance between adjacent through holes belonging to different sub-groups of through holes is selected such that said portion of semiconductor substrate separating the cavities formed beneath said different sub-groups has a width of at least about 1 μ
- m, preferably at least about 5 μ
m, more preferably at least about 10 μ
m, and most preferably between about 10 and 20 μ
m.
- m, preferably at least about 5 μ
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19. The method as claimed in claim 16 wherein further through holes between said first and second sub-groups of through holes are formed in said first dielectric layer;
- and wherein semiconductor substrate material is removed under said further through holes, thus forming at least one passage between said at least first and second cavities.
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20. The method as claimed in claim 16 wherein the number of sub-groups of through holes formed and the number of cavities formed beneath a single electrical device is at least 4, preferably at least 8, more preferably at least 12, and most preferably between 10 and 20.
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21. The method as claimed in claim 19 wherein the number of sub-groups of through holes formed and the number of cavities formed beneath a single electrical device is at least 4, preferably at least 8, more preferably at least 12, and most preferably between 10 and 20, and wherein said number of cavities and said at least one passage are formed such that said membrane above said number of cavities and said at least one passage is supported by semiconductor substrate material in the form of strings, walls, nets, pillars, or a framework.
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22. An electrical device structure, particularly an inductor structure for radio frequency (RF) applications, integrated in an integrated circuit (IC), wherein said electrical device structure is fabricated by using the method as claimed in claim 1.
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23. An integrated circuit, particularly an integrated circuit for radio frequency applications, wherein said integrated circuit comprises an electrical device structure as claimed in claim 22.
Specification