Method of fabricating integrated coil inductors for IC devices

• US 6,720,230 B2
• Filed: 09/10/2002
• Issued: 04/13/2004
• Est. Priority Date: 03/14/2001
• Status: Expired due to Term

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Rosner, Joanna, Cordes, Steven A., Groves, Robert A., Lund, Jennifer L., Carasso, Melanie L., Acosta, Raul E.
• Primary Examiner(s): Nguyen, Tuan H.
• Application Number:
  US10/238,746
• Publication Number:
  US 20030011041A1
• Time in Patent Office: 581 Days
• Field of Search: 438/381, 438/329, 438/238, 438/210, 438/3, 438/622, 438/638, 438/639, 438/640, 438/641, 336/200
• US Class Current: 438/381
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 17/0033 with the coil helically wound around a magnetic core
• CPC Class Codes: H01F 41/041 Printed circuit coils apparatus or processes for manufacturing printed circuits in general H05K3/00
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 Inductors

Abstract

A means for fabrication of solenoidal inductors integrated in a semiconductor chip is provided. The solenoidal coil is partially embedded in a deep well etched into the chip substrate. The non-embedded part of the coil is fabricated as part of the BEOL metallization layers. This allows for a large cross-sectional area of the solenoid turns, thus reducing the turn-to-turn capacitive coupling. Because the solenoidal coils of this invention have a large diameter cross-section, the coil can be made with a large inductance value and yet occupy a small area of the chip. The fabrication process includes etching of a deep cavity in the substrate after all the FEOL steps are completed; lining said cavity with a dielectric followed by fabrication of the part of the coil that will be embedded by deposition of a conductive material metal through a mask; deposition of dielectric and planarization of same by CMP. After planarization the fabrication of the remaining part of the solenoidal coil is fabricated as part of the metallization in the BEOL (i.e. as line/vias of the BEOL). To further increase the cross section of the solenoidal coil part of it may be built by electrodeposition through a mask on top of the BEOL layers.

Claims

1. A method of fabricating a semiconductor structure comprising the steps of:

(a) forming one or more cavities in a substrate of an integrated circuit (IC) chip;

(b) forming a first dielectric material over said substrate including in said one or more cavities;

(c) removing said first dielectric material abutting said one or more cavities, while leaving said first dielectric material in said one or more cavities as a liner;

(d) forming a bottom coil element of a solenoidal coil in said one or more dielectric lined cavities;

(e) forming a second dielectric material over said substrate including said bottom coil element of said solenoidal coil;

(f) removing said second dielectric material over said substrate not containing said one or more cavities; and

(g) forming side coil elements and a top coil element of said solenoidal coil, wherein said top coil element is in electrical contact with said bottom coil element through said side coil elements.

2. The method of claim 1 wherein said one or more cavities are formed by lithography and etching.

3. The method of claim 1 wherein said substrate includes a passivating layer formed thereon.

4. The method of claim 1 wherein said first dielectric has a thickness of from about 1 to about 10 microns.

5. The method of claim 4 wherein said first dielectric has a thickness of from about 4 to about 5 microns.

6. The method of claim 1 wherein said first dielectric material is formed by a blanket deposition process.

7. The method of claim 1 wherein step (c) is carried out by a planarization process.

8. The method of claim 7 wherein said planarization process is chemical-mechanical polishing.

9. The method of claim 1 wherein said bottom coil element is formed by the steps of:

forming a liner/seed layer on said first dielectric material;

forming a patterned photoresist on said substrate wherein said patterned photoresist does not cover portions of said liner/seed layer in said cavity; and

depositing a conductive material onto said liner/seed layer.

10. The method of claim 9 wherein said conductive material is deposited by an electrodeposition process.

11. The method of claim 1 wherein said second dielectric material is formed by deposition.

12. The method of claim 1 wherein step (f) includes a planarization process.

13. The method of claim 12 wherein said planarization process is chemical-mechanical polishing.

14. The method of claim 1 wherein said side coil elements are formed by damascene or dual damascene processes.

15. The method of claim 1 wherein said side coil elements are formed by the steps of:

forming a dielectric over said substrate including said second dielectric material;

providing openings in said dielectric exposing portions of said bottom coil element; and

filling said openings with a conductive material.

16. The method of claim 1 wherein said top coil element is formed by deposition of a conductive material through a patterned mask.

17. The method of claim 16 wherein said deposition comprises electrodeposition.

18. The method of claim 1 wherein side coil elements are also formed in step (d) and step (g) only includes formation of said top coil element.