Method for forming a cantilever beam model micro-electromechanical system

• US 6,720,267 B1
• Filed: 03/19/2003
• Issued: 04/13/2004
• Est. Priority Date: 03/19/2003
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Hong, Gary, Chen, Anchor
• Primary Examiner(s): LE, DUNG ANH
• Application Number:
  US10/249,149
• Time in Patent Office: 391 Days
• Field of Search: 438/52-53, 438/459, 438/689-694, 257/415-417
• US Class Current: 438/694
• CPC Class Codes: B81B 2201/047 Optical MEMS not provided for in B81B2201/042 - B81B2201/045
• CPC Class Codes: B81C 1/0015 Cantilevers switches using MEMS H01H1/0036; electrostatic relays using micromechanics H01H59/0009; microelectro-mechanical resonators H03H9/02244

Abstract

A cantilever beam type micro-electromechanical system (MEMS) is formed on a substrate. Two first electrodes are formed in a first dielectric layer on the substrate and a waveguide line is formed between the first electrodes. A patterned sacrificial layer and an arm layer are formed on the substrate. Two second electrodes and a second dielectric layer are formed in the arm layer, and an optical grating is formed in the second dielectric layer. Finally, a cap layer is formed on the substrate, and the patterned sacrificial layer is removed.

Claims

1. A method for forming a cantilever beam model micro-electromechanical system (MEMS), the method comprising:

providing a semiconductor substrate comprising a heavily doped layer and a first dielectric layer formed within the semiconductor substrate;

forming at least two first conductors connected to a surface of the heavily doped layer in the first dielectric layer;

forming a second dielectric layer not connected to the surface of the heavily doped layer in the first dielectric layer between the first conductors;

forming a patterned sacrificial layer on the semiconductor substrate that covers the second dielectric layer, the first dielectric layer, and the first conductors;

forming a third dielectric layer on the semiconductor substrate that covers the patterned sacrificial layer;

forming a fourth dielectric layer not connected to a surface of the patterned sacrificial layer in the third dielectric layer;

forming at least two second conductors on the third dielectric layer corresponding to the underlying first conductors formed on two sides of the second dielectric layer;

etching the fourth dielectric layer to form a plurality of openings in the fourth dielectric layer;

forming a cap layer on the semiconductor substrate to cover the second conductors, the fourth dielectric layer, and the third dielectric layer; and

removing the patterned sacrificial layer.

2. The method of claim 1 further comprising a step of forming a glue layer on the first dielectric layer, the second dielectric layer, and the first conductors before forming the patterned sacrificial layer.

3. The method of claim 2 further comprising a step of removing the glue layer while removing the patterned sacrificial layer.

4. The method of claim 1 further comprising a step of forming a block layer on the patterned sacrificial layer, the first dielectric layer, the second dielectric layer, and the first conductors after forming the patterned sacrificial layer.

5. The method of claim 4 further comprising a step of removing the glue layer while removing the patterned sacrificial layer.

6. The method of claim 1 wherein the third dielectric layer further comprises a first oxide layer and a second oxide layer, and a top surface of the first oxide layer is substantially aligned with a top surface of the patterned sacrificial layer.

7. The method of claim 1 wherein a method of removing the patterned sacrificial layer is an isotropic wet etching process.

8. The method of claim 7 further comprising an etching process to form a plurality of etch holes in the third dielectric layer for removing the patterned sacrificial layer uniformly and rapidly by the wet etching process before removing the patterned sacrificial layer.

9. The method of claim 1 wherein a refractive index (RI) of the first dielectric layer is different from an RI of the second dielectric layer and an RI of the third dielectric layer is different from an RI of the fourth dielectric layer.

10. The method of claim 1 wherein the first conductors and the second conductors both comprise gold (Au), tungsten (W), copper (Cu), aluminum (Al), Al—

Cu alloy, polysilicon, or other conductive materials.

11. The method of claim 1 wherein the patterned sacrificial layer comprises tungsten (W), silicon nitride, silicon oxide, organic polymer, or porous silicon.

12. The method of claim 1 wherein the cap layer is an oxide layer.

13. The method of claim 1 wherein the openings formed in the fourth dielectric layer have equal intervals, equal width, as well as equal depth.

14. A method for forming a cantilever beam model micro-electromechanical system (MEMS), the method comprising:

providing a semiconductor substrate comprising a heavily doped layer and a first dielectric layer formed within the semiconductor substrate;

forming at least two electrodes connected to a surface of the heavily doped layer in the first dielectric layer;

forming a waveguide line not connected to the surface of the heavily doped layer in the first dielectric layer between the first electrodes;

forming a patterned sacrificial layer on the semiconductor substrate that covers the waveguide line, the first dielectric layer, and the first electrodes;

forming an arm layer on the semiconductor substrate that covers the patterned sacrificial layer;

forming at least two second electrodes in the arm layer corresponding to the underlying first electrodes formed on two sides of the waveguide line;

forming a second dielectric layer not connected to a surface of the patterned sacrificial layer in the arm layer;

etching the second dielectric layer to form an optical grating in the second dielectric layer;

forming a cap layer on the semiconductor substrate to cover the second electrodes, the second dielectric layer, and the optical grating; and

isotropic etching the patterned sacrificial layer to form a cavity under the arm layer.

15. The method of claim 14 further comprising a step of forming a glue layer on the first dielectric layer, the waveguide line and the first electrodes before forming the patterned sacrificial layer.

16. The method of claim 15 further comprising a step of removing the glue layer while removing the patterned sacrificial layer.

17. The method of claim 14 further comprising a step of forming a block layer on the patterned sacrificial layer, the first dielectric layer, the waveguide line, and the first electrodes after forming the patterned sacrificial layer.

18. The method of claim 17 further comprising a step of removing the block layer while removing the patterned sacrificial layer.

19. The method of claim 14 wherein the arm layer further comprises an anchor layer and an oxide layer, and wherein a top surface of the anchor layer is substantially aligned with a top surface of the patterned sacrificial layer, and the oxide layer covers the patterned sacrificial layer and the anchor layer.

20. The method of claim 14 wherein the waveguide line, the arm layer, and the top layer are all made of oxide.

21. The method of claim 14 wherein a refractive index (RI) of the first dielectric layer is different from an RI of the waveguide line and an RI of the second dielectric layer is different from an RI of the arm layer.

22. The method of claim 14 wherein the first electrodes and the second electrodes both comprise gold (Au), tungsten (W), copper (Cu), aluminum (Al), Al—

Cu alloy, polysilicon, or other conductive materials.

23. The method of claim 14 wherein the patterned sacrificial layer comprises tungsten (W), silicon nitride, silicon oxide, organic polymer, or porous silicon.

24. The method of claim 14 wherein the optical grating further comprises a plurality of openings with equal intervals, equal width as well as equal depth, and the openings do not connect to the patterned sacrificial layer.

25. The method of claim 14 wherein the method of etching the patterned sacrificial layer is an isotropic wet etching process.

26. The method of claim 25 further comprising a dry etching process to form a plurality of etch holes for removing the patterned layer uniformly and rapidly before etching the patterned sacrificial layer.