Apparatus for high sensitivity, low lag, high voltage swing in a pixel cell with an electronic shutter

• US 6,720,592 B1
• Filed: 06/29/2001
• Issued: 04/13/2004
• Est. Priority Date: 06/29/2001
• Status: Expired due to Term

• Current Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Kindt, Willem Johannes, Lindorfer, Philipp
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): Sefer, Ahmed N.
• Application Number:
  US09/895,803
• Time in Patent Office: 1,019 Days
• Field of Search: 257/231, 257/239, 257/292, 257/444, 250/208.1
• US Class Current: 257/231
• CPC Class Codes: H01L 27/14601 Structural or functional details thereof

Abstract

The present invention is directed to a photogate based pixel cell with an electronic shutter and which provides relatively low lag and high sensitivity for sensing infrared light reflected from objects. Additionally, this invention eliminates the need for a transfer gate in the pixel cell. In one embodiment, the reset and shutter transistors are implemented with PMOS transistors so that the pixel cell can have an increased dynamic range and a relatively high voltage swing. In another embodiment, the actual size of each pixel cell can be further reduced when the reset gate and the electronic shutter are implemented with NMOS transistors. Also, when a P− well is not disposed beneath the photogate, the ability of the pixel cell to sense infrared light is improved. Correlated double sampling can be used to improve the accuracy of the signal read out from the pixel cell.

Claims

1. A circuit for a pixel cell, comprising:

(a) a photogate disposed over a P−

substrate, wherein electrons collect in a region underneath the photogate when a potential on the photogate is high and light is incident on the photogate;

(b) an N+ floating diffusion area disposed adjacent to the photogate on the surface of the P−

substrate and a first and a second capacitance coupled to opposite sides of a shutter transistor, the N+ floating diffusion area and the first and second capacitances storing electrons that migrate from underneath the photogate when the potential on the photogate is low;

(c) a reset transistor coupled between the N+ floating diffusion area and a supply voltage, wherein the electrons stored in the N+ floating diffusion area move to the supply voltage when the reset transistor conducts; and

(d) a first transistor having a gate coupled to the shutter transistor and the N+ floating diffusion area, wherein when the shutter transistor is non-conducting, a signal voltage representing light incident on the photogate is stored on the second capacitance that is coupled to one side of the shutter transistor and also coupled to the gate of the first transistor, so that the signal voltage is presented at the gate of the first transistor for read out.

2. The circuit of claim 1, wherein when the shutter transistor is conducting, the electrons stored in the first and second capacitances and the N+ floating diffusion area are converted into the signal voltage.

3. The circuit of claim 2, wherein the first capacitance and second capacitance include parasitic capacitance, source capacitance of the reset transistor, channel capacitance of the shutter transistor and the junction capacitance of the N+ floating diffusion area.

4. The circuit of claim 1, wherein the reset transistor and the shutter transistor are PMOS devices, the PMOS devices enabling a large voltage swing inside the pixel cell and greater dynamic range for the signal voltage.

5. The circuit of claim 1, wherein the reset transistor and the shutter transistor are NMOS devices, the NMOS devices enabling a small size for the pixel cell.

6. The circuit of claim 1, further comprising a P−

well that is disposed adjacent to and around the circumference of the photogate, the P−

well providing lateral confinement for electrons collected underneath the photogate and the absence of the P−

well beneath the photogate enables electrons induced by infrared light to collect underneath the photogate.

7. The circuit of claim 1, further comprising a circuit that employs at least a correlated double sampling method to read out the signal voltage.

8. The circuit of claim 1, further comprising an image sensor that includes a plurality of pixel cells arranged in a grid.

9. The circuit of claim 1, further comprising a source follower circuit, the source follower circuit includes the first transistor and a second transistor, wherein when the second transistor conducts, the signal voltage is available for read out.

10. A circuit for a pixel cell, comprising:

(a) a photogate disposed over a P−

substrate, wherein electrons collect in a region underneath the photogate when a potential on the photogate is high and light is incident on the photogate;

(b) an N+ floating diffusion area disposed adjacent to the photogate on the surface of the P−

substrate and a first and a second capacitance coupled to opposite sides of a shutter switch, the N+ floating diffusion area and the first and second capacitances storing electrons that migrate from underneath the photogate when the potential on the photogate is low;

(c) a reset switch coupled between the N+ floating diffusion area and a supply voltage, wherein the electrons stored in the N+ floating diffusion area move to the supply voltage when the reset switch closes; and

(d) a first transistor having a gate coupled to the shutter switch and the N+ floating diffusion area, wherein when the shutter switch is open, a signal voltage representing light incident on the photogate is stored on the second capacitance that is coupled to one side of the shutter switch and also coupled to the gate of the first transistor, so that the signal voltage is presented at the gate of the first transistor for read out.

11. The circuit of claim 10, wherein when the shutter switch is closed, the electrons stored in the second capacitance are converted into the signal voltage.

12. The circuit of claim 10, wherein the reset switch and the shutter switch are PMOS devices.

13. The circuit of claim 10, wherein the first capacitance and the second capacitance include parasitic capacitance, source capacitance of the reset switch, channel capacitance of the shutter switch and the junction capacitance of the N+ floating diffusion area.

14. A pixel cell circuit, comprising:

(a) means for collecting charges underneath a photogate when the photogate is active, a shutter is open and light is incident on the photogate;

(b) means for storing electrons comprising a first means for storing electrons that is arranged to store electrons on a first side of the shutter, and a second means for storing electrons that is arranged to store electrons on a second side of the shutter, wherein the electrons migrate from beneath the photogate to the means for storing electrons when the photogate is inactive and the shutter is closed, and wherein the first side of the shutter is coupled to the photogate when the shutter is open;

(c) means for closing the shutter to isolate a storage node on one side of the shutter;

(d) a signal voltage that is related to the charge of the stored electrons, the signal voltage being representative of the amount of light incident on the photogate when the shutter is closed; and

(e) means for reading out the signal voltage.

15. The pixel cell circuit as in claim 14, wherein the first means for storing electrons comprises a first capacitor, and the second means for storing electrons comprises a second capacitor.

16. The pixel cell circuit as in claim 14, wherein the pixel cell circuit further comprises a means for removing photo-induced charges that is arranged to remove photo-induced charges from underneath the photogate during a store period, such that a node at the first side of the shutter discharges during the store period, and wherein the means for reading out the signal voltage is configured to read out the signal voltage from the second side of the shutter during the store period.