Image sensor array with reduced pixel crosstalk

• US 6,720,594 B2
• Filed: 01/07/2002
• Issued: 04/13/2004
• Est. Priority Date: 01/07/2002
• Status: Expired due to Term

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Inventors: Lu, Jeng Ping, Rahn, Jeffrey T., Van Schuylenbergh, Koenraad F.
• Primary Examiner(s): Dickey, Thomas L
• Application Number:
  US10/041,544
• Publication Number:
  US 20030127672A1
• Time in Patent Office: 827 Days
• Field of Search: 257/291-293, 257/443, 257/444, 250/208.1, 250/214.R, 250/214.1, 250/370-1-3, 348/302-308, 348/158, 348/187, 348/246, 348/296, 348/298, 348/311, 348/312
• US Class Current: 257/291
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14658 X-ray, gamma-ray or corpuscular radiation imagers measuring X-, gamma- or corpuscular radiation G01T1/00
• CPC Class Codes: H01L 31/1055 the devices comprising amorphous materials of Group IV of the Periodic Table

Abstract

Improved pixel circuits are disclosed for high fill-factor large area imager systems using continuous (e.g., amorphous silicon) sensor layers. A first approach prevents crosstalk by ensuring that each pixel is not able to go into saturation. A second approach employs a cascode transistor to maintain the bias of the sensor contact at a constant potential regardless of illumination condition. These two approaches may be combined. A resistive film connecting the pixel contacts may be used in conjunction with the second approach to prevent aliasing of signal and noise.

Claims

1. An imager system comprising

a scanning control circuit for generating gate voltage signals on a plurality of gate lines;

a continuous sensor layer;

a bias voltage source; and

a plurality of pixels arranged in an array, each pixel including;

a sensor including an associated portion of the continuous sensor layer and having a first terminal connected to the bias voltage source, the sensor also having a second terminal;

a storage capacitor having a first terminal coupled to the second terminal of the sensor, and a second terminal connected to a system voltage source; and

an access transistor having a first terminal connected to the first terminal of the storage capacitor, a second terminal connected to an associated data line, and a gate terminal coupled to an associated gate line of the plurality of gate lines controlled by the scanning control circuit;

wherein the imager system further comprises means connected to at least one of the sensor and the access transistor of each of said plurality of pixels for controlling a voltage across the sensor of each of the plurality of pixels such that the sensor of each of the plurality of pixels is prevented from reaching saturation.

2. The imager system according to claim 1,

wherein the second terminal of said each sensor comprises a first metal plate contacting a first region of the associated portion of the continuous sensor layer, and the first terminal of said each sensor comprises a transparent biasing layer formed on a second region of the associated portion of the continuous censor layer,

wherein the storage capacitor comprises a second metal plate connected to the first metal plate, and a third metal plate located below the second metal plate,

wherein the transparent biasing layer is connected to the bias voltage source, and

wherein the third metal plate is connected to the system voltage source.

3. The imager system according to claim 1,

wherein said scanning control circuit generates a first voltage signal on a selected gate line to turn on the access transistor of a selected pixel during a first operating period, and generates a second voltage signal on the selected gate line to turn off the access transistor of the selected pixel during a second operating period,

wherein the bias voltage source generates the bias voltage at a voltage level that differs from the second voltage signal generated by the gate line control circuit by at least one threshold voltage of the access transistor.

4. The imager system according to claim 1,

wherein said scanning control circuit generates a first gate signal on a first gate line connected to a first pixel and a second gate signal on a second gate line connected to a second pixel, both the first and second pixels being connected to an associated data line,

wherein the first gate signal includes a first voltage pulse in which the first gate line is changed from a first voltage level to a second voltage level at a first operating times,

wherein the second gate signal includes a second voltage pulse in which the second gate line is changed from the first voltage level to the second voltage level at a second operating time, and

wherein both the first and second gate signals include a third voltage pulse at a third operating time that is between the first operating time and the second operating time, and changes the first and second gate lines from the first voltage level to a third voltage level that is between the first voltage level and the second voltage level.

5. The imager system according to claim 1, wherein said means comprises a clamp transistor connected between the system voltage source and the second terminal of the sensor.

6. The imager system according to claim 5,

wherein said scanning control circuit generates a first voltage signal on a selected gate line to turn on the access transistor of a selected pixel during a first operating period, and generates a second voltage signal on the selected gate line to turn off the access transistor of the selected pixel during a second operating period, and

wherein the imager system further comprises means connected to a gate terminal of the clamp transistor for generating a clamp voltage having a voltage level that differs from the bias voltage signal generated by the bias voltage source by at least one threshold voltage of the clamp transistor.

7. The imager system according to claim 1, wherein said means comprises a cascode transistor connected between the first terminal of the storage capacitor and the second terminal of the sensor.

8. The imager system according to claim 7,

wherein said scanning control circuit generates a first voltage signal on a selected gate line to turn on the access transistor of a selected pixel during a first operating period, and generates a second voltage signal on the selected gate line to turn off the access transistor of the selected pixel during a second operating period, and

wherein the imager system further comprises means connected to a gate terminal of the cascade transistor for generating a clamp voltage having a voltage level that differs from the bias voltage by at least one threshold voltage of the cascade transistor.

9. The imager system according to claim 7,

wherein said sensor comprises a first metal plate, a sensor layer formed on the first metal plate, and a transparent biasing layer formed on the sensor layer,

wherein the storage capacitor comprises the second metal plate and a third metal plate located below the second metal plate,

wherein the cascode transistor is connected between the first metal plate and the second metal plate, and

wherein the access transistor is formed between the second metal plate and the associated data line.

10. The imager system according to claim 9,

wherein the first metal plate is formed from a first metal layer,

wherein the second metal plate is formed from a second metal layer located below the first metal layer,

wherein the third metal plate is formed from a third metal layer located below the second metal layer,

wherein the cascode transistor comprises a first metal portion formed from the second metal layer, the first metal portion being connected to the first metal plate by a metal via structure, the cascode transistor also including a first gate portion located under a channel separating the first metal portion and the second metal plate, the first gate portion being formed from the third metal layer, and

wherein the access transistor comprises a second gate portion located under a channel separating the second metal portion and the associated data line, the second gate portion being formed from the third metal layer.

11. The imager system according to claim 9, wherein the sensor layer comprises an amorphous silicon layer including a plurality of spaced-apart lower doped regions,

each lower doped region being formed over the first metal plate of an associated pixel, a continuous undoped layer extending over the plurality of pixels, and an upper Continuous doped region abutting the transparent biasing layer.

12. The imager system according to claim 11, wherein the plurality of spaced-apart lower doped regions comprise relatively high doping concentrations, and wherein the sensor layer further comprises a resistor region connecting the plurality of lower doped regions, the resistor region comprising a relatively low doping concentration.

13. The imager system according to claim 9, wherein the sensor comprises a photoresistive material selected from the group consisting of Se, PbI₂, and HgI.

14. The imager system according to claim 7, further comprising a clamp transistor connected between the system voltage source and the second terminal of the sensor.

15. An imager system comprising;

a scanning control circuit for generating gate voltage signals on a plurality of gate lines;

a continuous sensor layer;

a bias voltage source; and

a plurality of pixels arranged in an array, each pixel including;

a sensor including an associated portion of the continuous sensor layer and having a first terminal connected to the bias voltage source, the sensor also having a second terminal;

a storage capacitor having a first terminal coupled to the second terminal of the sensor, and a second terminal connected to a system voltage Source;

an access transistor having a first terminal connected to the first terminal of the storage capacitor, a second terminal connected to an associated data line, and a gate terminal coupled to an associated gate line of the plurality of gate lines controlled by the scanning control circuit; and

a clamp transistor connected across the storage capacitor between the system voltage source and the second terminal of the sensor.

16. The imager system according to claim 15,

wherein the second terminal of said each sensor comprises a first metal plate contacting a first region of the associated portion of the continuous sensor layer, and the first terminal of said each sensor comprises a transparent biasing layer formed on a second region of the associated portion of the continuous sensor layer,

wherein the storage capacitor comprises a second metal plate connected to the first metal plate, and a third metal plate located below the second metal plate,

wherein the transparent biasing layer is connected to the bias voltage source, and

wherein the third metal plate is connected to the system voltage source.

17. The imager system according to claim 15,

wherein said scanning control circuit generates a first voltage signal on a selected gate line to turn on the access transistor of a selected pixel during a first operating period, and generates a second voltage signal on the selected gate line to turn off the access transistor of the selected pixel during a second operating period, and

wherein the imager system further comprises means connected to a gate terminal of the clamp transistor for generating a clamp voltage having a voltage level that is at least one threshold voltage above the bias voltage signal generated by the bias voltage source.

18. The imager system according to claim 15, further comprising a cascode transistor connected between the storage capacitor and the second terminal of the sensor.

19. An imager System comprising:

a scanning control circuit for generating gate voltage signals on a plurality of gate lines;

a continuous sensor layer;

a bias voltage source; and

a plurality of pixels arranged in an array, each pixel including;

a sensor having an first terminal connected to a bias voltage source, the sensor also having a second terminal;

a storage capacitor including an associated portion of the continuous sensor layer and having a first terminal coupled to the second terminal of the sensor and a second terminal connected to a system voltage source;

an access transistor having a first terminal connected to the first terminal of the storage capacitor, a second terminal connected to an associated data line, and a gate terminal coupled to an associated gate line of the plurality of gate lines controlled by the scanning control circuit; and

a cascode transistor connected between the first terminal of the storage capacitor and the second terminal of the sensor.

20. The imager system according to claim 19,

wherein said scanning control circuit generates a first voltage signal on a selected gate line to turn on the access transistor of a selected pixel during a first operating period, and generates a second voltage signal on the selected gate line to turn off the access transistor of the selected pixel during a second operating period, and

wherein the imager system further comprises means connected to a gate terminal of the cascode transistor for generating a clamp voltage having a voltage level that differs from the bias voltage by at least one threshold voltage of the cascode transistor.

21. The imager system according to claim 19,

wherein said sensor comprises a first metal plate,

wherein said continuous sensor layer is formed on the first metal plate,

wherein a transparent biasing layer is formed on the continuous sensor layer,

wherein the storage capacitor comprises the second metal plate and a third metal plate located below the second metal plate,

wherein the cascode transistor is connected between the first metal plate and the second metal plate, and

wherein the access transistor is formed between the second metal plate and the associated data line.

22. The imager system according to claim 19,

wherein the first metal plate is formed from a first metal layer,

wherein the second metal plate is formed from a second metal layer located below the first metal layer,

wherein the third metal plate is formed from a third metal layer located below the second metal layer,

wherein the cascode transistor comprises a first metal portion formed from the second metal layer, the first metal portion being connected to the first metal plate by a metal via structure, the cascode transistor also including a first gate portion located under a channel separating the first metal portion and the second metal plate, the first gate portion being formed from the third metal layer, and

wherein the access transistor comprises a second gate portion located under a channel separating the second metal portion and the associated data line, the second gate portion being formed from the third metal layer.

23. The imager system according to claim 19, wherein the continuous sensor layer comprises an amorphous silicon layer including a plurality of spaced-apart lower doped regions, each lower doped region being formed over the first metal plate of an associated pixel, a continuous undoped layer extending over the plurality of pixels, and an upper continuous doped region abutting the transparent biasing layer.

24. The imager system according to claim 23, wherein the plurality of spaced-apart lower doped regions comprise relatively high doping concentrations, and wherein the continuous sensor layer further comprises a resistor region connecting the plurality of lower doped regions, the resistor region comprising a relatively low doping concentration.

25. The imager system according to claim 19, wherein the sensor comprises a photoresistive material selected from the group consisting of Se, PbI₂, and HgI.

26. An imager system comprising:

a scanning control circuit for generating gate voltage signals on a plurality of gate lines;

a continuous layer of sensor material including a plurality of spaced-apart, relatively highly doped regions, a continuous undoped layer formed over the plurality of relatively highly doped regions, and a continuous doped layer formed over the undoped layer;

a bias voltage source; and

a plurality of pixels arranged in an array, each pixel including;

a sensor including an associated portion of the continuous layer of sensor material sensor and having a first terminal connected to a bias voltage source, the sensor also having a pixel contact abutting an associated highly doped region of the plurality of spaced apart highly doped regions;

a storage capacitor having a first terminal and a second terminal, the second terminal being connected to a system voltage source;

an access transistor having a first terminal connected to the first terminal of the storage capacitor, a second terminal connected to an associated data line, and a gate terminal coupled to an associated gate line of the plurality of gate lines controlled by the scanning control circuit; and

a cascode transistor connected between the first terminal of the storage capacitor and the second terminal of the sensor,

wherein the continuous layer further comprises a resistor region formed below the continuous undoped layer and contacting the plurality of spaced-apart, relatively highly doped regions, and

wherein the resistor region has a doping level greater than the continuous undoped layer and less than the plurality of spaced-apart, relatively highly doped regions.