Trench MOS transistor

• US 6,720,616 B2
• Filed: 12/26/2001
• Issued: 04/13/2004
• Est. Priority Date: 06/25/1999
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Larik, Joost, Hirler, Franz, Pfirsch, Frank, Kotek, Manfred
• Primary Examiner(s): Jackson, Jerome
• Assistant Examiner(s): LANDAU, MATTHEW C
• Application Number:
  US10/027,531
• Publication Number:
  US 20020093050A1
• Time in Patent Office: 839 Days
• Field of Search: 257/328, 257/331, 257/339, 257/341, 257/302, 257/330, 257/333, 257/335, 257/296
• US Class Current: 257/330
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench MOS-transistor includes a body region strengthened by an implantation area that faces the drain region to increase the avalanche resistance.

Claims

1. A trench MOS transistor, comprising:

a semiconductor body with a first conductivity type forming at least one drain zone and formed of a semiconductor substrate and an epitaxial layer on said substrate, said epitaxial layer and said substrate having a junction therebetween;

said semiconductor body having;

a trench ending in a vicinity of said junction and having;

a gate electrode;

a trench side area contacting a side face of said trench;

a trench upper end; and

a trench lower end extending into said semiconductor body;

at least one source zone with said first conductivity type, said source zone;

disposed in said trench side area at said trench upper end; and

having a source lower end;

a first region with a second conductivity type disposed in said trench side area between said trench and an adjacent trench, said first region having a dopant gradient; and

a second region with said second conductivity type, said second region;

buried in said first region in said trench side area;

having a higher doping and a steeper dopant gradient than said first region;

disposed between said source zone and said drain zone;

shaped in a strip; and

having a charge carrier concentration of between 10¹⁷ to 10¹⁹ charge carriers/cm³;

an insulating layer electrically isolating said gate electrode from said source zone, said first region, and said drain zone; and

said insulating layer having a step forming;

a first layer portion having a given thickness at said trench lower end; and

a second layer portion having a thickness smaller than said given thickness at said trench upper end.

2. The trench MOS transistor according to claim 1, wherein said step is beveled.

3. The trench MOS transistor according to claim 1, wherein said second region is ion implanted.

4. The trench MOS transistor according to claim 1, wherein:

said second region is disposed at a distance between said trench and the adjacent trench; and

said second region is parallel to said trench and the adjacent trench.

5. The trench MOS transistor according to claim 1, wherein said second region runs perpendicular to said trench.

6. The trench MOS transistor according to claim 1, wherein said second region runs perpendicular to said trench and the adjacent trench.

7. The trench MOS transistor according to claim 1, wherein said trench ends in a vicinity of said junction.

8. The trench MOS transistor according to claim 1, wherein said first conductivity type is a p-conductivity type.

9. A trench MOS transistor configuration, comprising:

a semiconductor body with a first conductivity type forming at least one drain zone and formed of a semiconductor substrate and an epitaxial layer on said substrate, said epitaxial layer and said substrate having a junction therebetween;

said semiconductor body having;

trenches ending in a vicinity of said junction and each having;

a gate electrode;

a trench side area contacting a side face of said trench;

a trench upper end; and

a trench lower end extending into said body;

at least one source zone with said first conductivity type, said source zone;

disposed in said trench side area at said trench upper end; and

having a source lower end;

a first region with a second conductivity type disposed in said trench side area between said trench and an adjacent trench, said first region having a dopant gradient; and

a second region with said second conductivity type, said second region;

buried in said first region in said trench side area;

having a higher doping and a steeper dopant gradient than said first region;

disposed between said source zone and said drain zone;

shaped in a strip; and

having a charge carrier concentration of between 10¹⁷ to 10¹⁹ charge carriers/cm³;

at least one insulating layer electrically isolating said gate electrode from said source zone, said first region, and said drain zone; and

said insulating layer having a step forming;

a first layer portion having a given thickness at said trench lower end; and

a second layer portion having a thickness smaller than said given thickness at said trench upper end.