Transistor having a deposited dual-layer spacer structure

• US 6,720,631 B2
• Filed: 10/20/1997
• Issued: 04/13/2004
• Est. Priority Date: 12/11/1995
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Hussein, Makarem A., Cotner, Raymond E., Brigham, Lawrence N.
• Primary Examiner(s): Nguyen, Cuong
• Application Number:
  US08/954,430
• Publication Number:
  US 20010042894A1
• Time in Patent Office: 2,367 Days
• Field of Search: 257/407, 257/900, 257/382-408, 257/344-346, 438/238-239, 438/300-305
• US Class Current: 257/408
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

A transistor comprising a deposited dual-layer spacer structure and method of fabrication. A polysilicon layer is deposited over a gate dielectric, and is subsequently etched to form the polysilicon gate electrode of the transistor. Next, oxide is deposited over the surface of the gate electrode, followed by deposition of a second dielectric layer. Spacers are then formed adjacent to the gate electrode by etching back the second dielectric layer using a substantially anisotropic etch which etches the second dielectric layer faster than it etches the oxide.

Claims

1. A transistor comprising:

a gate dielectric disposed over a semiconductor substrate;

a gate electrode disposed over said gate dielectric, said gate electrode having laterally opposed sidewalls;

a pair of tip regions disposed within said semiconductor substrate adjacent to said gate electrode, said pair of tip regions being shallow, heavily doped, and substantially aligned to said sidewalls of said gate electrode;

a pair of spacer structures disposed adjacent to said gate electrode, said pair of spacer structures being deposited and comprising;

a first layer, said first layer covering said sidewalls of said gate electrode and said semiconductor substrate adjacent to said sidewalls; and

a second layer, said second layer covering said first layer; and

a pair of source/drain regions within said semiconductor substrate adjacent to said pair of spacer structures, wherein a supply voltage of less than 5 volts is coupled to said pair of source/drain regions to reduce hot electron charging effects in said gate dielectric to acceptable levels.

2. The transistor of claim 1 wherein said second layer has a thickness of less than 100 Å

.

3. The transistor of claim 1 wherein said first layer has a thickness of less than 50 Å

.

4. The transistor of claim 1 wherein said first layer has a thickness of 50-300 Å

and said second layer has a thickness of less than 500 Å

.

5. The transistor of claim 1 wherein the implant dose used to form said pair of tip regions is at least 0.5 order of magnitude less than the implant dose used to form said pair of source/drain regions.

6. The transistor of claim 1 wherein said gate dielectric comprises oxide and nitride.

7. The transistor of claim 1 wherein said gate electrode has a width of less than 0.1 um.

8. The transistor of claim 1 wherein the lower corners of said gate electrode lie predominantly flat and square with the surface of said semiconductor substrate.

9. The transistor of claim 1 therein said pair of spacer structures further comprises a third layer.

10. The transistor of claim 9 wherein said third layer comprises one or more of the following:

oxide, nitride, oxynitride, polysilicon, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), organic materials such as polyimide.

11. The transistor of claim 9 wherein said third layer is disposed below said first layer.

12. The transistor of claim 9 wherein said third layer is disposed above said second layer.

13. The transistor of claim 1 wherein said pair of spacer structures separates suicide regions disposed over said gate electrode and over said source/drain regions.

14. The transistor of claim 1 further comprising:

a second gate dielectric disposed over said gate electrode, and

a second gate electrode disposed over said second gate dielectric.

15. A transistor comprising:

a gate dielectric disposed over a semiconductor substrate;

a gate electrode disposed over said gate dielectric;

a pair of heavily-doped (n+) tip regions disposed within said semiconductor substrate adjacent to said gate electrode;

a pair of deposited spacer structures disposed over said pair of heavily-doped (n+) tip regions; and

a pair of source/drain regions disposed within said semiconductor substrate adjacent to said pair of heavily-doped (n+) tip regions, said tip regions being extensions of said source/drain regions.

16. The transistor of claim 15 wherein the pair of deposited spacer structures comprises oxide with a thickness of less than 50 Å

and nitride with a thickness of less than 500 Å

.