Multilevel interconnect structure with low-k dielectric

• US 6,720,655 B1
• Filed: 10/11/2000
• Issued: 04/13/2004
• Est. Priority Date: 06/13/1997
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Primary Examiner(s): Lee, Eddie
• Assistant Examiner(s): Owens, Douglas W.
• Application Number:
  US09/685,855
• Time in Patent Office: 1,280 Days
• Field of Search: 257/750, 257/751, 257/753, 257/758, 257/759, 257/762, 257/765
• US Class Current: 257/751
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A multilevel interconnect structure with a low-k dielectric constant is fabricated in an integrated circuit structure by the steps of depositing a layer of photoresist on a substrate assembly, etching the photoresist to form openings, forming a metal layer on the photoresist layer to fill the openings and then removing the photoresist layer by, for example, ashing. The metal layer is supported by the metal which filled the openings formed in the photoresist.

Claims

1. A semiconductor device comprising:

a substrate assembly; and

at least one interconnect structure on said substrate assembly, said interconnect structure comprising;

a first bilayer defining a first receptacle;

a first metal plug formed in said first receptacle;

a second bilayer defining a second receptacle above said first metal plug;

a metal layer having a portion elevated above said substrate assembly and a portion filling said second receptacle such that said metal layer is in electrical contact with said substrate assembly, and wherein said bilayers are selected from the group consisting of titanium/copper, chromium/copper, titanium nitride/copper, tantalum/copper, W/copper and WN/copper;

a gas surrounding said first and second receptacles; and

a low-k dielectric film on said metal layer.

2. A semiconductor device of claim 1 wherein said gas is air.

3. A semiconductor device of claim 2 wherein said low-k dielectric film has a dielectric constant of about 1 to about 2.5.

4. A semiconductor device of claim 2 wherein said low-k dielectric film has a dielectric constant of about 1 to 2.0.

5. A semiconductor device of claim 4 wherein said low-k dielectric film comprises one of an aerogel and a xerogel.

6. A semiconductor device of claim 2 wherein said metal plugs at metal layer are formed of a copper containing material.

7. A semiconductor device of claim 2 where said metal layer has a thickness of from about 0.5 micron to about 1.0 micron.

8. The semiconductor device of claim 2 wherein said dielectric film has a dielectric constant of from about 1 to about 2.5.

9. The semiconductor device of claim 2 wherein said dielectric films has a dielectric constant of from about 1 to about 2.0.

10. The semiconductor device of claim 2 wherein said dielectric film is selected from the group consisting of aerogels and xerogels.

11. The semiconductor device of claim 2 wherein the metal layer comprise copper and has a thickness of from about 0.5 micron to about 1.0 micron.

12. The semiconductor device of claim 2 wherein said substrate assembly comprises a lower insulation substrate, a plurality of lower planar metal contacts recessed in said lower insulation substrate, and respective diffusion barrier layers deposited on said lower insulation substrate and said metal contacts.

13. The semiconductor device of claim 12 wherein a diffusion barrier layer of Si₃N₄ is provided over said lower insulation substrate, and a diffusion barrier layer of TiN is provided over said metal contacts.

14. The semiconductor device of claim 2 wherein said first and second bilayers are selected from the group consisting of W/copper and WN/copper.

15. The semiconductor device of claim 2 wherein said dielectric film has a dielectric constant of from about 1 to about 2.5.

16. The semiconductor device of claim 2 wherein said dielectric films has a dielectric constant of from about 1 to about 2.0.

17. The semiconductor device of claim 2 wherein said dielectric film is selected from the group consisting of aerogels and xerogels.

18. The semiconductor device of claim 2 wherein the metal layer comprise copper and has a thickness of from about 0.5 micron to about 1.0 micron.

19. A semiconductor device comprising:

a substrate assembly;

a metal layer in electrical contact with at least a portion of said substrate assembly, said metal layer comprising a portion elevated above said substrate assembly;

a metal component in electrical contact with said metal layer and said at least a portion of said substrate assembly, said metal component supporting said elevated portion of said metal layer;

an adhesion promoter/diffusion barrier bilayer between said metal layer and said metal component, wherein said adhesion promoter/diffusion barrier bilayer is selected from the group consisting of titanium/copper, chromium/copper, titanium nitride/copper, tantalum/copper, W/copper and WN/copper;

a gas surrounding said metal component; and

a low-k dielectric film on said metal layer.

20. The semiconductor device of claim 19, herein said metal component comprises at least one metal plug.

21. The semiconductor device of claim 19, wherein said metal component comprises at least one metal contact.