PWM controller regulating output voltage and output current in primary side
First Claim
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1. A PWM controller for regulating an output voltage and an output current in a primary side circuit, the PWM controller comprising:
- a feedback synthesizer for generating a feedback voltage in response to a supply voltage, wherein the supply voltage is supplied by an auxiliary winding of a transformer for powering the PWM controller;
wherein the feedback voltage varies in inverse proportion to the supply voltage;
an adaptive load circuit for producing an adaptive load current to keep a supply current as a constant by means of compensation, wherein the supply current is sourced by the supply voltage for powering the PWM controller;
a programmable power limiter for generating a limit voltage, wherein the limit voltage varies in direct proportion to the supply voltage;
an oscillator for outputting a pulse signal;
a first AND-gate having a first input terminal, a second input terminal and an output terminal;
a RS flip-flop for generating an on-off signal, wherein the RS flip-flop is set by the pulse signal and reset by an output of the first AND-gate;
a second AND-gate having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the second AND-gate is supplied with the pulse signal, the second input terminal of the second AND-gate is supplied with the on-off signal, and the output terminal of the second AND-gate supplies a PWM signal for switching the transformer;
a first comparator having a positive input terminal, a negative input terminal and an output terminal, wherein the positive input terminal of the first comparator is supplied with the feedback voltage, and the negative input terminal of the first comparator is supplied with a current-sense voltage, wherein the current-sense voltage is converted from a switching current of the transformer; and
a second comparator having a positive input terminal, a negative input terminal and an output terminal, wherein the positive input terminal of the second comparator is supplied with the limit voltage and the current-sense voltage is supplied to the negative input terminal of the second comparator, wherein an on-time of the PWM signal increases in direct proportion to the feedback voltage wherein the on-time of the PWM signal decreases in direct proportion to the limit voltage.
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Abstract
A PWM controller according to the present invention provides a technique to control the output voltage and output current of the power supply without the feedback control circuit in the secondary side of the transformer. In order to achieve better regulation, an adaptive load and a feedback synthesizer are equipped into the PWM controller, which associated with the auxiliary winding of the transformer regulate the output voltage of the power supply as a constant. Furthermore, a programmable power limiter in the PWM controller controls the power that is delivered from the primary side to the output of the power supply. The threshold of the power limit is varied in accordance with the change of output voltage. Because the output power is the function of the output voltage of the power supply, a constant current output is realized when the output current of the power supply is greater than a maximum value.
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Citations
4 Claims
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1. A PWM controller for regulating an output voltage and an output current in a primary side circuit, the PWM controller comprising:
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a feedback synthesizer for generating a feedback voltage in response to a supply voltage, wherein the supply voltage is supplied by an auxiliary winding of a transformer for powering the PWM controller;
wherein the feedback voltage varies in inverse proportion to the supply voltage;
an adaptive load circuit for producing an adaptive load current to keep a supply current as a constant by means of compensation, wherein the supply current is sourced by the supply voltage for powering the PWM controller;
a programmable power limiter for generating a limit voltage, wherein the limit voltage varies in direct proportion to the supply voltage;
an oscillator for outputting a pulse signal;
a first AND-gate having a first input terminal, a second input terminal and an output terminal;
a RS flip-flop for generating an on-off signal, wherein the RS flip-flop is set by the pulse signal and reset by an output of the first AND-gate;
a second AND-gate having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the second AND-gate is supplied with the pulse signal, the second input terminal of the second AND-gate is supplied with the on-off signal, and the output terminal of the second AND-gate supplies a PWM signal for switching the transformer;
a first comparator having a positive input terminal, a negative input terminal and an output terminal, wherein the positive input terminal of the first comparator is supplied with the feedback voltage, and the negative input terminal of the first comparator is supplied with a current-sense voltage, wherein the current-sense voltage is converted from a switching current of the transformer; and
a second comparator having a positive input terminal, a negative input terminal and an output terminal, wherein the positive input terminal of the second comparator is supplied with the limit voltage and the current-sense voltage is supplied to the negative input terminal of the second comparator, wherein an on-time of the PWM signal increases in direct proportion to the feedback voltage wherein the on-time of the PWM signal decreases in direct proportion to the limit voltage. - View Dependent Claims (2, 3, 4)
a first resistor;
a first operational amplifier having a positive input terminal, a negative input terminal and an output terminal, wherein the positive input terminal of the first operational amplifier is supplied with a reference voltage, and the negative input terminal of the first operational amplifier is coupled to the first resistor;
a first transistor having a gate coupled to the output terminal of the first operational amplifier, a source coupled to the first resistor, and a drain for generating a reference current;
a first current mirror for generating a first current, wherein the first current is constant;
a third current mirror for generating a third current, wherein the third current is also constant;
a fourth current mirror for generating a drain-output current;
a fifth current mirror for generating a fifth current;
a Zener diode having an anode and a cathode, wherein the cathode of the Zener diode is supplied with the supply voltage;
a second resistor;
a second operational amplifier having a positive input terminal, a negative input terminal and an output terminal, wherein the positive input terminal of the second operational amplifier is connected to the anode of the Zener diode, and the negative input terminal of the second operational amplifier is coupled to the second resistor;
a third resistor coupled to the positive input terminal of the second operational amplifier; and
a second transistor having a gate coupled to the output terminal of the second operational amplifier, a source coupled to the second resistor, and a drain for generating a feedback current, wherein the feedback current varies in direct proportion to the supply voltage; and
a fourth resistor for converting the drain-output current into the feedback voltage, wherein the feedback voltage varies in inverse proportion to the feedback current.
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3. The PWM controller as claimed in claim 1, wherein the adaptive load circuit comprises:
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a second current mirror for generating a second current, wherein the second current is constant;
a sixth current mirror for generating a sixth current;
an eighth current mirror for generating an input-mirror current from the sixth current; and
a seventh current mirror for subtracting the input-mirror current from the second current and producing the adaptive load current, wherein the adaptive load current varies in inverse proportion to the feedback current.
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4. The PWM controller as claimed in claim 1, wherein the programmable power limiter comprises:
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a third operational amplifier having a positive input terminal, a negative input terminal and an output terminal;
a divider composed of a fifth resistor and a sixth resistor, wherein a first terminal of the fifth resistor is supplied with the supply voltage, wherein a second terminal of the sixth resistor is connected to a ground reference, wherein a second terminal of the fifth resistor and a first terminal of the sixth resistor are connected to the positive input terminal of the third operational amplifier;
a seventh resistor;
a third transistor having a gate coupled to the output terminal of the third operational amplifier, a source coupled to the seventh resistor, and a drain for generating a left-mirror current;
wherein the left-mirror current varies in direct proportion to the supply voltage;
a ninth current mirror having a left-transistor and a right-transistor for generating a right-mirror current from the left-mirror current;
wherein a source of the left-transistor and a source of the right-transistor are connected together;
wherein a drain of the left-transistor is connected to a gate of the left-transistor and a gate of the right-transistor, wherein the right-mirror current is generated via a drain of the right-transistor;
a first current source, wherein an input terminal of the first current source is supplied with the supply voltage, wherein an output terminal of the first current source is connected to the source of the left-transistor;
a second current source, wherein an input terminal of the second current source is supply with the supply voltage, wherein an output terminal of the second current source is connected to the drain of the right-transistor; and
an eighth resistor for converting a sum-current into the limit voltage, wherein the sum-current is obtained from summing an output current of the second current source and the right-mirror current.
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Specification
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Current AssigneeFairchild Taiwan Corp (ON Semiconductor Corporation)
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Original AssigneeSystem General Corporation (ON Semiconductor Corporation)
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InventorsYang, Ta-yung, Chen, Chern-Lin, Lin, Jenn-yu G., Leu, Yi-Hsin
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Primary Examiner(s)Sherry, Michael
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Assistant Examiner(s)Laxton, Gary L.
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Application NumberUS10/249,214Time in Patent Office386 DaysField of Search363/21.01, 363/21.04, 363/21.05, 363/21.09, 363/21.1, 363/21.11, 363/21.12, 363/21.13, 363/21.17, 363/21.18, 363/97, 363/131US Class Current363/21.18CPC Class CodesH01F 2038/026 non-linear inductive arrang...H02M 1/0025 Arrangements for modifying ...H02M 3/33507 with automatic control of t...
