Semiconductor memory device

• US 6,721,223 B2
• Filed: 05/15/2002
• Issued: 04/13/2004
• Est. Priority Date: 06/15/2001
• Status: Expired due to Fees

• Current Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Yamauchi, Tadaaki, Matsumoto, Junko, Okamoto, Takeo
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US10/145,191
• Publication Number:
  US 20020191467A1
• Time in Patent Office: 699 Days
• Field of Search: 365/222, 365/236, 365/230.03
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays

Abstract

Data specifying details of refresh to be executed in the self-refresh mode is stored in a register circuit in a mode register. A refresh period and refresh region are determined according to data stored in register circuit and a refresh control circuit generates a control signal and a refresh address that are required for refresh. Stored data can be stably held in the self-refresh mode in which data holding is performed with reduced current consumption.

Claims

1. A semiconductor memory device comprising:

a memory array having a plurality of memory cells;

refresh circuitry for refreshing storage data of a memory cell in said memory array;

a register circuit for storing data setting at least one of a refresh period and a refresh region of said memory array, said register circuit storing externally applied refresh specifying data in response to an externally applied register set instruction signal; and

refresh execution control circuitry for generating, in refresh execution, a refresh address specifying a memory cell to be refreshed in said memory array, and supplying said refresh address to and activating said refresh circuitry, according to data stored in said register circuit, wherein

said refresh specifying data comprises region specifying data specifying a refresh target region of said memory array to be refreshed, and

said refresh execution control circuitry includes;

a counter for generating a counter address in a refresh operation mode of performing the refresh; and

a circuit for modifying the counter address in accordance with the region specifying data to change the counter address into an address in said refresh target region to generate said refresh address.

2. The semiconductor memory device according to claim 1, wherein said refresh execution control circuitry comprises a refresh period adjustment circuit for setting said refresh period according to said region specifying data.

3. The semiconductor memory device according to claim 2, wherein said refresh period adjustment circuit comprises:

an oscillation circuit having an operating frequency determined according to said region specifying data; and

a circuit for counting an oscillation signal outputted from said oscillation circuit to generate a refresh request requesting refresh of data in said memory array.

4. The semiconductor memory device according to claim 1, wherein

said register circuit stores the data indicating the refresh region, and

said refresh execution control circuitry comprises:

a refresh period program circuit storing data indicating a period at which refresh of stored data in a memory cell of said memory array by means of a fuse programming, said refresh period program circuit being activated in a self-refresh mode, for outputting the programmed refresh period data; and

a refresh request generation circuit for outputting a refresh request requesting execution of refresh according to the stored, programmed refresh period data.

5. The semiconductor memory device according to claim 1, wherein the refresh specifying data comprises data indicating a temperature compensated, refresh period at which refresh is performed.

6. The semiconductor memory device according to claim 1, wherein said memory array comprises a plurality of memory blocks each having a plurality of memory cells, and

said refresh execution control circuitry comprises:

a refresh address generation circuit for generating the refresh address specifying a memory cell in said memory array; and

a refresh block address holding circuit for setting a refresh block address, specifying a memory block to be refreshed in said a plurality of memory blocks, included in the refresh address generated by said refresh address generation circuit in a state of designating a same memory block over a plurality of refresh cycles in a self-refresh mode.

7. The semiconductor memory device according to claim 1, wherein said memory array is divided into a plurality of memory subblocks each having a plurality of memory cells arranged in rows and columns, the memory subblocks aligned in a row direction constituting a row block, and

said semiconductor memory device further comprises:

a plurality of subword lines, provided corresponding to the respective memory cell rows of each of said memory subblocks, each having memory cells on a corresponding row connected, and

said refresh execution control circuitry includes;

a count circuit for performing a count operation to determine the number of times of refresh in a self-refresh mode;

a circuit for generating subdecode signals specifying a subword line in the subword lines according to said refresh address; and

a subword line reset circuit for activating a subdecode signal specifying a non-selected subword line in said subdecode signals according to a count outputted from said count circuit to drive a corresponding non-selected subword line to a reset state.

8. The semiconductor memory device according to claim 7, further comprising:

sense amplifier circuits, each disposed between adjacent row blocks of said row blocks, each for sensing and amplifying data in memory cells of a corresponding row block when activated; and

a plurality of bit line isolation circuit, disposed between the respective row blocks and corresponding sense amplifier circuits, each for electrically connecting a corresponding row block to a corresponding sense amplifier circuit when made conductive, and

said refresh execution control circuitry further includes,

a refresh bit line resetting circuit for driving the bit line isolation circuits to a reset state according to the count outputted from said count circuit to turn a bit line isolation circuit in a non-conductive state into a conductive state.

9. The semiconductor memory device according to claim 8, wherein said memory array is divided into a plurality of banks activated independently of each other, and said refresh bit line resetting circuit and said subword line resetting circuit are provided corresponding to each respective bank.

10. The semiconductor memory device according to claim 1, wherein said refresh execution control circuitry comprises:

a refresh address generation circuit for generating the refresh address specifying a memory cell to be refreshed in said memory array; and

a refresh region fixing circuit for fixing in logic level a prescribed address bit of said refresh address in a self-refresh mode.

11. The semiconductor memory device according to claim 1, wherein said memory array is divided into a plurality of memory subblocks each having a plurality of memory cells arranged in rows and columns, the memory subblocks aligned in a column direction constitute a column block, and the memory subblocks aligned in a row direction constitute a row block, and

said semiconductor memory device further comprises:

a plurality of local data lines, provided corresponding to the respective memory subblocks, each electrically coupled to a selected column Of a corresponding column block;

a plurality of main data lines, provided corresponding to the column blocks, each electrically coupled to a selected memory subblock of a corresponding column block; and

a block select circuit for coupling, in accordance with a row block specifying signal, a local data line provided corresponding to a memory subblock of a corresponding row block to a corresponding main data line in an normal operation mode, and for isolating, in a self-refresh mode, said local data line from the corresponding main data line.

12. The semiconductor memory device according to claim 1, wherein said register circuit storing data setting a 4 K refresh cycle scheme set as a default data value to an 8 K refresh cycle scheme in application of a mode register set command.

13. The semiconductor memory device according to claim 1, wherein the stored data in said register circuit is reset according to external data in response to application of a second mode register set command.

14. The semiconductor memory device according to claim 1, wherein said register circuit makes the stored data set therein later valid.

15. A semiconductor memory device comprising:

a plurality of banks, each having a plurality of memory cells arranged in rows and columns, driven to a selected state independently of each other;

refresh address generation circuitry for generating a refresh address for refreshing memory cells of said plurality of banks in a refresh operation, said refresh address generation circuitry including a circuit for generating a refresh bank address specifying a bank of said plurality of banks, said refresh bank address specifying a part of said plurality of banks in a low power consumption mode, and specifying all the banks in a mode different from said low power consumption mode; and

refresh execution control circuitry for executing refresh on a memory cell of a bank specified by the refresh address from said refresh address generation circuitry.

16. The semiconductor memory device according to claim 15, wherein said a plurality of banks are arranged in alignment along a first direction and a second direction perpendicular to said first direction and

said refresh address simultaneously selects banks adjacent in a direction different from the first and second directions in said low power consumption mode.

17. The semiconductor memory device according to claim 15, wherein each bank includes a plurality of memory blocks each having the memory cells arranged in rows and columns, and

said refresh execution control circuitry comprises a circuit, provided corresponding at least to each group of banks selected simultaneously, for driving a selected memory block to a non-selected state in a corresponding bank according to a count of an address counter, included in said refresh address generation circuitry, generating said refresh address.

18. The semiconductor memory device according to claim 15, wherein said refresh execution control circuitry comprises:

a control circuit for generating a refresh control signal for activating an operation of refreshing memory cell data in the refresh mode; and

a refresh circuit for refreshing memory cell data of a selected bank in response to said refresh control signal, said refresh control signal being held in an inactive state in a normal operation mode other than said refresh mode.

19. The semiconductor memory device according to claim 15, further comprising a plurality of internal voltage generation circuits, provided corresponding to the respective banks, each generating an internal power supply voltage from an external power supply voltage onto a corresponding internal power supply line when activated, the internal power supply line provided for each respective bank being interconnected together to be provided commonly to said plurality of banks, wherein

said refresh execution control circuitry activates all the internal power supply voltage generation circuits in the refresh mode of operation.