Circuit and method for reducing memory idle cycles

• US 6,721,233 B2
• Filed: 02/11/2003
• Issued: 04/13/2004
• Est. Priority Date: 08/21/2000
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Wilford, John R., Pawlowski, Joseph T.
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Nguyen, Tuan T.
• Application Number:
  US10/365,233
• Publication Number:
  US 20030161206A1
• Time in Patent Office: 427 Days
• Field of Search: 365/233, 365/230.02, 365/230.03, 365/189.02, 365/189.04, 365/189.05
• US Class Current: 365/189.02
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters

Abstract

An N-bit wide synchronous, burst-oriented Static Random Access Memory (SRAM) reads out a full N bits simultaneously from its array in accordance with an address A0 into N latched sense amplifiers, which then sequentially output N/X bit words in X burst cycles. Because the SRAM'"'"'s array reads out the full N bits simultaneously, the array'"'"'s address bus is freed up to latch in the next sequential address A1 so data output continues uninterrupted, in contrast to certain conventional SRAMs. The SRAM also writes in a full N bits simultaneously after sequentially latching in N/X bit words in X burst cycles into N write drivers. This simultaneous write frees up the array'"'"'s address bus to begin latching in the next sequential address A1 so data input continues uninterrupted, again in contrast to certain conventional SRAMs.

Claims

1. A circuit for retrieving a plurality of sequentially stored data bits from an N-bit wide memory array comprising:

address circuitry configured for coupling with the memory array and for latching an address of a first one of the plurality of sequentially stored data bits and for generating burst addresses from two or more least significant bits of the address;

storage circuitry coupled to the memory array for temporarily storing N data bits from the memory array as designated by the address, the N data bits including the plurality of sequentially stored data bits; and

multiplexing circuitry coupled to the storage circuitry for sequentially transferring the sequentially stored data bits from the storage circuitry as sequenced by the burst addresses.

2. The circuit, as recited in claim 1, further comprising pass circuitry coupled between the storage circuitry and the memory array for selecting the sequentially stored data bits from among the N data bits for passing to the multiplexing circuitry.

3. The circuit, as recited in claim 1, wherein the storage circuitry comprises at least one latched sense amplifier for each of the sequentially stored data bits.

4. The circuit, as recited in claim 1, wherein the address circuitry comprises:

an address register for registering the address of the first one of the plurality of sequentially stored data bits; and

burst control logic coupled to the multiplexing circuitry and the address register and externally supplied control signals for generating the burst addresses.

5. The circuit, as recited in claim 1, wherein the multiplexing circuitry includes a plurality of multiplexers for transferring the sequentially stored data bits in sequence in accordance with the address followed by the burst addresses.

6. The circuit, as recited in claim 1, further comprising circuitry coupled to the storage circuitry for directing the storage circuitry to simultaneously transfer the N data bits between a selected N-bit wide row of the memory array and the storage circuitry.

7. The circuit, as recited in claim 1, further configured for coupling with a memory array configured as a Static Random Access Memory (SRAM).

8. The circuit, as recited in claim 1, further comprising data I/O circuitry for coupling with the multiplexing circuitry for transmitting data.

9. A method for retrieving multiple pluralities of sequentially stored data bits from a memory array, comprising:

registering a first address in an address register for a first stored data bit of a first plurality of sequentially stored data bits and generating burst addresses from the first address for other data bits of the first plurality of sequentially stored data bits;

simultaneously sensing from the memory array the first plurality of sequentially stored data bits;

sequentially outputting the first stored data bit of the first plurality of sequentially stored data bits followed by the other data bits of the first plurality of sequentially stored data bits; and

prior to outputting all of the other data bits of the first plurality of sequentially stored data bits, repeating the method with a second address of a second plurality of sequentially stored data bits.

10. The method, as recited in claim 9, wherein the sequentially outputting comprises sequentially multiplexing the first stored data bit and the other data bits of the first plurality of sequentially stored data bits according to the first address and the burst addresses.

11. The method, as recited in claim 9, wherein the repeating further comprises adjacently aligning sequential outputting of a last data bit of the first plurality of sequentially stored data bits with sequentially outputting a first stored data bit of the second plurality of sequentially stored data bits.