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Switch-based scalable performance computer memory architecture

  • US 6,721,317 B2
  • Filed: 01/02/2002
  • Issued: 04/13/2004
  • Est. Priority Date: 03/04/1999
  • Status: Expired due to Term
First Claim
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1. A data switch, comprising;

  • a memory unit for storing frame header substitution information, wherein the frame header substitution information comprises a substitute destination address;

    a plurality of ports, wherein each of the plurality of ports is adapted for coupling to a transmission medium;

    an array of switching elements for selectively coupling the plurality of ports to one another;

    a switch matrix control unit coupled to receive routing information from the plurality of ports and configured to control the array of switching elements dependent upon the routing information;

    wherein the data switch is configured to receive frame header substitution information on one of the plurality of ports and to store the frame header substitution information within the memory unit; and

    wherein the data switch is further configured to;

    (i) receive a data frame on a port other than the port on which the frame header substitution information was received, wherein the data frame comprises header information including a destination address, (ii) replace the header information of the data frame with the substitute header information stored within the memory unit such that the substitute destination address becomes a new destination address, and (iii) provide the new destination address to the switch matrix control unit as the routing information.

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