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One sample per symbol high rate programmable parallel architecture for digital demodulation

  • US 6,721,371 B1
  • Filed: 01/05/2000
  • Issued: 04/13/2004
  • Est. Priority Date: 02/25/1999
  • Status: Expired due to Term
First Claim
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1. A high speed demodulator system comprising:

  • an analog to digital converter (ADC);

    a high speed demultiplexer connected to an output of the ADC;

    a bank of parallel programmable demodulators connected to an output of the high speed demultiplexer;

    a timing interface connected to the bank of parallel programmable demodulators, the timing interface providing signal timing information to a first demodulator in the bank of demodulators, the first demodulator adapted to output a signal to the analog to digital converter for controlling a frequency and timing of the analog to digital converter to allow the bank of demodulators to lock on and track a received signal; and

    a phase reference interface connected to the bank of parallel programmable demodulators and a data processor to provide phase information on phases of demodulated data from each demodulator, each demodulator tracking a different phase of the received signal.

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