One sample per symbol high rate programmable parallel architecture for digital demodulation

• US 6,721,371 B1
• Filed: 01/05/2000
• Issued: 04/13/2004
• Est. Priority Date: 02/25/1999
• Status: Expired due to Term

• Current Assignee: L-3 Communications Corporation (L3Harris Technologies, Inc.)
• Original Assignee: L-3 Communications Corporation (L3Harris Technologies, Inc.)
• Inventors: Barham, Steven T, Bagley, Zachary C, Horne, Lyman D
• Primary Examiner(s): Tran, Khai
• Assistant Examiner(s): TRAN, KHANH C
• Application Number:
  US09/477,882
• Time in Patent Office: 1,560 Days
• Field of Search: 375/130, 375/143-144, 375/147, 375/148-150, 375/260, 375/271, 375/275, 375/280, 375/316, 375/322, 375/325, 375/340, 375/343, 375/355, 375/362, 375/367, 329/315-316, 329/323, 329/327, 329/341, 329/345, 329/346, 329/358, 329/363, 370/320, 370/328, 370/335, 370/342, 370/344, 370/441, 370/480, 370/481, 370/484, 370/515, 370/516, 370/535, 370/536, 370/537, 370/542, 370/543, 370/544, 455/313, 455/314, 455/334-335, 455/338, 455/337
• US Class Current: 375/316
• CPC Class Codes: H03H 17/0294 Variable filters; Programmable filters
• CPC Class Codes: H04L 25/03006 Arrangements for removing intersymbol interference

Abstract

A high speed demodulator system is comprised of an analog to digital converter (ADC); a high speed demultiplexer connected to an input of the ADC; a bank of parallel programmable demodulators connected to an output of the high speed demultiplexer; a timing interface connected to the bank of parallel programmable demodulators; and a phase reference interface connected to the bank of parallel programmable demodulators and a data processor. A parallel programmable demodulator includes a reconfigurable FIR filter, has an input port for receiving digital input signals and an output coupled to a coherent signal processor and a coherent memory. The programmable FIR filter provides filtered signals to the coherent signal processor for storage in the coherent memory. The integrated circuit further includes a sequential weight processor having an input coupled to an output of the coherent memory. The sequential weight processor includes a weight memory and operates to output symbol soft decision data resulting from processing the digital input signals. The integrated circuit is programmable into one of a plurality of operating modes, including at least one of a received signal acquisition mode, a channel estimator mode, an adaptive equalizer mode, and a channel-wise differential mode.

Claims

1. A high speed demodulator system comprising:

an analog to digital converter (ADC);

a high speed demultiplexer connected to an output of the ADC;

a bank of parallel programmable demodulators connected to an output of the high speed demultiplexer;

a timing interface connected to the bank of parallel programmable demodulators, the timing interface providing signal timing information to a first demodulator in the bank of demodulators, the first demodulator adapted to output a signal to the analog to digital converter for controlling a frequency and timing of the analog to digital converter to allow the bank of demodulators to lock on and track a received signal; and

a phase reference interface connected to the bank of parallel programmable demodulators and a data processor to provide phase information on phases of demodulated data from each demodulator, each demodulator tracking a different phase of the received signal.

2. A high speed demodulator system as in claim 1, wherein the high speed demultiplexer further comprises:

a demultiplexer operating at N times a received symbol rate, wherein N is equal to the number of parallel programmable ASIC demodulators in the bank.

3. A high speed demodulator system as in claim 1, wherein the bank of parallel programmable demodulators further comprises an array of programmable application specific integrated circuits (ASICs), wherein each ASIC further comprises an integrated circuit, comprising a reconfigurable multistage FIR filter having an input for receiving digital input signals and an output coupled to a coherent signal processor and a coherent memory for providing filtered signals thereto, the integrated circuit further comprising an adaptive weight processor having an input coupled to an output of said coherent memory, the adaptive weight processor comprising a weight memory and outputting symbol soft decision data resulting from processing the digital input signals.

4. A high speed demodulator system as in claim 1, wherein the timing interface further comprises a timing interface connected to an output of each of the parallel programmable demodulators, and to an input of at least one of the parallel programmable demodulators.

5. A high speed demodulator system as in claim 1, wherein the phase reference interface further comprises a phase reference connected to an output of each of the parallel programmable demodulators.

6. A high speed demodulator system as in claim 1, wherein the bank of parallel programmable demodulators further comprises an array of field programmable gate arrays.

7. The system of claim 1 wherein each demodulator comprises a rapid acquisition dispersive channel receiver integrated circuit demodulator.

8. The system of claim 1 wherein the timing interface is adapted to sample one sample per demodulated signal and provide signal timing information to a first demodulator in the bank of demodulators.

9. A method for acquiring information signals from an analog transmission signal, the method comprising steps of:

receiving the analog transmission signal;

mixing the analog transmission signal to produce a first analog signal and a second analog signal;

digitizing the first analog signal to provide a first stream of digitized signals (I stream);

digitizing the second analog signal to provide a second stream of digitized signals (Q stream);

demultiplexing the I and Q streams of digitized signals to an array of programmable demodulators, the array of programmable demodulators having a first programmable demodulator, wherein each of the programmable demodulators further comprises an application specific integrated circuit (ASIC), comprising a reconfigurable multistage FIR filter having an input for receiving digital input signals and an output coupled to a coherent signal processor and a coherent memory for providing filtered signals thereto, the integrated circuit further comprising an adaptive weight processor having an input coupled to an output of said coherent memory, the adaptive weight processor comprising a weight memory and outputting symbol soft decision data resulting from processing the digital input signals.

10. A method according to claim 9, wherein the step of collecting and synchronizing the plurality of outputs of the array of programmable demodulators further comprises the steps of:

providing a phase reference interface between the plurality of outputs of the array of programmable demodulators and a data processor; and

providing a timing interface between the plurality of outputs of the array of programmable demodulators and the analog to digital converter (ADC).

11. A method according to claim 10, wherein the step of providing the timing interface further comprises the steps of:

sampling the plurality of outputs of the array of programmable demodulators; and

providing an error signal responsive to the sampled plurality of outputs of the array of programmable demodulators to the first programmable demodulator; and

providing a correction signal from the first programmable demodulator to an analog to digital converter in response to the error signal.

12. A method according to claim 10, wherein the step of providing the phase reference interface further comprises the steps of:

sampling the phase of the plurality of outputs of the array of programmable demodulators; and

providing phase reference information responsive to the sampling of the phase of the plurality of outputs of the array of programmable demodulators to the data processor.

13. A method according to claim 10 wherein the steps of collecting and synchronizing the output of the array of programmable demodulators further comprises the steps of:

connecting a data processor to accept a plurality of outputs of the array of programmable demodulators and a plurality of outputs from the phase reference interface; and

reconstituting an information signal responsive to the plurality of outputs from the phase reference interface.

14. A method according to claim 9, further comprising the steps of:

digitizing an M number of the first analog signal and the second analog signal through an analog to digital converter (ADC) to provide an M number of the I stream digitized signals and an M number of the Q stream digitized signals, wherein M is equal to a received symbol rate;

providing the M number of the I stream digitized signals and the M number of the Q stream digitized signals to a demultiplexer;

demultiplexing the M number of the I stream digitized signals and the Q stream digitized signals at N times the received symbol rate to provide an array of N demultiplexed outputs, wherein N is equal to the number of the arrayed programmable demodulators; and

providing the array of N demultiplexed outputs to the array of programmable demodulators.

15. A method according to claim 9, further comprising the steps of:

digitizing the first analog signal and the second analog signal through an analog to digital converter (ADC) to provide the I stream and the Q stream digitized signals;

providing the I stream digitized signals and the Q stream digitized signals to a demultiplexer;

demultiplexing the I stream digitized signals and the Q stream digitized signals at a multiple of the received symbol rate to providing an array of demultiplexed outputs, wherein the number of demultiplexed outputs is equal to the number of the arrayed programmable demodulators; and

providing the array of demultiplexed outputs to the array of programmable demodulators.

16. A method of high rate demodulation of a series of modulated analog signals, the method comprising steps of:

acquiring and digitizing the series of modulated analog signals;

providing parallel programmable demodulation of the digitized series of modulated analog signals;

providing a plurality of parallel demodulated data; and

reorganizing the demodulated data by providing a plurality of samples of the plurality of parallel demodulated data to a timing interface, a data processor, and a phase reference interface;

sequencing the plurality of parallel demodulated data provided to the data processor according to a plurality of controls provided by a phase reference interface;

controlling timing of at least one of a plurality of demodulator application specific integrated circuits (ASICs) responsive to the plurality of samples of the plurality of parallel demodulated data; and

providing an output of at least one of the plurality of demodulator ASICS to an analog to digital converter.

17. A method according to claim 16, wherein the steps of acquiring and digitizing the series of modulated analog signals is further comprised of the step of:

digitizing the series of modulated analog signals through an analog to digital converter.

18. A method according to claim 16, wherein the step of providing parallel demodulation of the digitized series of modulated data is further comprised of the steps of:

sequentially demultiplexing the digitized series of modulated data to a plurality of parallel programmable application specific integrated circuits (ASIC) demodulators at a demultiplexer rate equal to the number of programmable demodulator ASICs; and

demodulating the digitized series of modulated data to a plurality of parallel demodulated data.

19. A method according to claim 16, further comprising programming a bank of parallel programmable application specific integrated circuits (ASICs) demodulators to demodulate a received modulation type, wherein each ASIC further comprises an integrated circuit, comprising a reconfigurable multistage FIR filter having an input for receiving digital input signals and an output coupled to a coherent signal processor and a coherent memory for providing filtered signals thereto, the integrated circuit further comprising an adaptive weight processor having an input coupled to an output of said coherent memory, the adaptive weight processor comprising a weight memory and outputting symbol soft decision data resulting from processing the digital input signals.

20. A high speed demodulator system comprising:

an analog to digital converter (ADC);

a high speed demultiplexer connected to an output of the ADC;

a bank of parallel programmable demodulators connected to an output of the high speed demultiplexer comprising an array of programmable application specific integrated circuits (ASICs), wherein each ASIC further comprises an integrated circuit, comprising a reconfigurable multistage FIR filter having an input for receiving digital input signals and an output coupled to a coherent signal processor and a coherent memory for providing filtered signals thereto, the integrated circuit further comprising an adaptive weight processor having an input coupled to an output of said coherent memory, the adaptive weight processor comprising a weight memory and outputting symbol soft decision data resulting from processing the digital input signals;

a timing interface connected to the bank of parallel programmable demodulators; and

a phase reference interface connected to the bank of parallel programmable demodulators and a data processor.