Image processing unit

• US 6,721,462 B2
• Filed: 01/26/2001
• Issued: 04/13/2004
• Est. Priority Date: 02/18/2000
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Okabayashi, Keiju, Sawasaki, Naoyuki
• Primary Examiner(s): Tran, Phuoc
• Application Number:
  US09/769,521
• Publication Number:
  US 20010022859A1
• Time in Patent Office: 1,173 Days
• Field of Search: 382/305, 382/278, 382/307, 382/209, 382/218, 382/181, 708/5, 708/422, 708/424, 708/490, 708/501, 708/605, 708/813, 707/6
• US Class Current: 382/278
• CPC Class Codes: G06F 17/153 Multidimensional correlation or convolution
• CPC Class Codes: G06T 2200/28 involving image processing hardware
• CPC Class Codes: G06T 2207/10016 Video; Image sequence
• CPC Class Codes: G06T 7/223 using block-matching

Abstract

In an image processing unit for performing an arithmetic operation between a reference image and a search image, a product-sum operation section comprises systoric array, a normalization and accumulation processing section and a correlation value memory control section. The product-sum operation section is used on a common basis for an operation for the addition of a square of a pixel value of a search image over a plurality of pixels and an operation for the addition of a multiplication of pixel values of pixels associated with the search image and the reference image over a plurality of pixels. An operation for a norm of the reference image is performed on a path (a reference image norm computing section) which is different from that of the product-sum operation section.

Claims

1. An image processing unit for performing an arithmetic operation between a reference image and a search image, upon receipt of the reference image and the search image, said image processing unit having an image processing section comprising:

a first multiplication section for computing a square of a pixel value of the reference image;

an addition section for adding square value of the pixel values of the reference image obtained by said first multiplication section over a plurality of pixels;

a first square root computing section for computing a square root of an additional value over a plurality of pixels of the square value of the pixel values of the reference image obtained by said addition section to determine a norm of the reference image;

a product-sum operation section used on a common basis for both an addition of square values of pixel values of the search image over a plurality of pixels and an addition of multiplication values of pixel values of pixels associated with the search image and the reference image over a plurality of pixels;

a second square root computing section for computing a square root of an additional value over a plurality of pixels of the square value of the pixel values of the search image obtained by said product-sum operation section to determine a norm of the search image;

a second multiplication section for multiplying the norm of the reference image obtained by said first square root computing section and the norm of the search image obtained by said second square root computing section together; and

a division section for dividing an additional value of multiplication values of pixel values of pixels associated with the search image and the reference image over a plurality of pixels obtained by said product-sum operation section by a multiplication value between the norm of the reference image and the norm of the search image obtained by said second multiplication section to obtain a normalization correlation value.

2. An image processing unit according to claim 1, wherein said first multiplication section and said second multiplication section are used on a common basis by a single multiplication section.

3. An image processing unit according to claim 1, wherein said first square root computing section and said second square root computing section are used on a common basis by a single square root computing section.

4. An image processing unit according to claim 1, wherein said product-sum operation section has a mode in which instead of the addition of multiplication values of pixel values of pixels associated with the search image and the reference image over a plurality of pixels, an addition of absolute values of differences between pixel values of pixels associated with the search image and the reference image over a plurality of pixels is performed.

5. An image processing unit according to claim 1, wherein said division section has a mode in which instead of a division by a multiplication value between the norm of the reference image and the norm of the search image obtained, a division is performed by a predetermined constant.

6. An image processing unit according to claim 5, wherein said image processing section further comprises an absolute value computing section for computing an absolute value of a value obtained by said division section.

7. An image processing unit according to claim 1, wherein said image processing section further comprises a peak detection section for detecting a peak position on the search image as to the normalization correlation value obtained by said division section.

8. An image processing unit according to claim 7, wherein said product-sum operation section has a mode in which instead of the addition of multiplication values of pixel values of pixels associated with the search image and the reference image over a plurality of pixels, an addition of absolute values of differences between pixel values of pixels associated with the search image and the reference image over a plurality of pixels is performed, and

said peak detection section detects a peak position on the search image as to the addition of absolute values in said mode.

9. An image processing unit according to claim 1, wherein said product-sum operation section has a systoric array for performing an operation between all of a plurality of bits representative of one pixel value when pixel values are expressed by a plurality of bits, and a part of bits belonging to one group when a plurality of bits representative of another pixel value is divided into a plurality of groups, and said systoric array assembles an operation result between said one pixel value and said another pixel value in accordance with a plurality of operation results obtained through a sequential operation on said plurality of groups.

10. An image processing unit according to claim 1, wherein said image processing section further comprises:

a first fixed-point achieving processing section for providing such a processing that when the additional value of the square value of the pixel values of the reference image over a plurality of pixels, which are obtained by said addition section, is such a small value that zeros are put at an upper significant bit end of a plurality of bits representative of the additional value, the additional value represented by the plurality of bits is shifted to the upper significant bit end so that a decimal point position is shifted to the upper significant bit end to transfer the same to said first square root computing section;

a second fixed-point achieving processing section for providing such a processing that when the additional value of the square value of the pixel values of the search image over a plurality of pixels, which are obtained by said product-sum operation section, is such a small value that zeros are put at an upper significant bit end of a plurality of bits representative of the additional value, the additional value represented by the plurality of bits is shifted to the upper significant bit end so that a decimal point position is shifted to the upper significant bit end to transfer the same to said second square root computing section; and

a third fixed-point achieving processing section for providing such a processing that the additional value of multiplication values of pixel values of pixels associated with the search image and the reference image over a plurality of pixels, which are obtained by said product-sum operation section, said additional value being expressed by a plurality of bits, is shifted to the upper significant bit end by a shift amount according to a shift amount in said first fixed-point achieving processing section and a shift amount in said second fixed-point achieving processing section so that a decimal point position is shifted to the upper significant bit end to transfer the same to said division section.

11. An image processing unit according to claim 1, wherein said image processing section repeats by a plurality of number of times a partial operation according to a part of data of data representative of the reference image and the search image so that an operation according to the reference image and the search image are completed,

and wherein said image processing section further comprises:

a cache memory for storing the search image; and

a memory control section for providing such a control that while data representative of the search image is stored in said cache memory, data necessary for a partial operation for the first time of data representative of the search image is transferred to said image processing section, and with respect to two or more partial operations based on the same search image, necessary data is read from said cache memory to transfer the same to said image processing section.

12. An image processing unit according to claim 1, wherein said image processing unit further comprises a image memory having a plurality of frame memories each for storing a frame of search image, and a memory control section for providing such a control that the plurality of frame memories are used on a circulation basis so that an entered search image is stored in each of the frame memories one frame by one frame.

13. An image processing unit according to claim 1, wherein said image processing section comprises an operation command storage section for sequentially storing a plurality of operation commands, and an operation result storage section for sequentially storing a plurality of operation results, and said image processing section derives the operation command from said operation command storage section to perform an arithmetic operation in accordance with the operation command and causes a result of the arithmetic operation to be stored in said operation result storage section,

said image processing unit further comprises an image processing control section having two modes of a first mode in which the operation command is fed to said image processing section so as to be stored in said operation command storage section, and a second mode in which the operation result stored in said operation result storage section is derived, and

said image processing control section changes over from the first mode to the second mode when said operation result storage section is full, and changes over from the second mode to the first mode when said operation command storage section is empty.