High-speed on-chip windowed centroiding using photodiode-based CMOS imager

• US 6,721,464 B2
• Filed: 01/03/2003
• Issued: 04/13/2004
• Est. Priority Date: 09/30/1999
• Status: Expired due to Term

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Yang, Guang, Pain, Bedabrata, Sun, Chao, Cunningham, Thomas J., Hancock, Bruce
• Primary Examiner(s): Mehta, Bhavesh M.
• Assistant Examiner(s): PATEL, KANJIBHAI B
• Application Number:
  US10/336,701
• Publication Number:
  US 20030133625A1
• Time in Patent Office: 466 Days
• Field of Search: 382/205, 382/288, 382/305, 382/312, 382/315, 348/294, 348/297, 348/298, 348/302, 348/308, 348/309, 348/310
• US Class Current: 382/312
• CPC Class Codes: G06T 5/20 using local operators
• CPC Class Codes: G06T 7/66 of image moments or centre of gravity
• CPC Class Codes: H04N 25/626 Reduction of noise due to residual charges remaining after image readout, e.g. to remove ghost images or afterimages
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors

Abstract

A centroid computation system is disclosed. The system has an imager array, a switching network, computation elements, and a divider circuit. The imager array has columns and rows of pixels. The switching network is adapted to receive pixel signals from the image array. The plurality of computation elements operates to compute inner products for at least x and y centroids. The plurality of computation elements has only passive elements to provide inner products of pixel signals the switching network. The divider circuit is adapted to receive the inner products and compute the x and y centroids.

Claims

1. An integrated semiconductor device, comprising:

a photodiode, responsive to radiation to produce charge and having a sensing node to output said charge;

an output transistor having a gate coupled to said sensing node to produce a pixel signal representing said charge; and

a reset transistor having a source formed from said sensing node, a gate coupled to receive a reset signal, and a drain coupled to a separate reset control signal which is pulsed on and off when said reset signal remaine on to reset said sensing node and to erase a memory in said photodiode from a previous readout cycle.

2. The device as in claim 1, further comprising a selection transistor coupled to said output transistor to receive said pixel signal and having a gate that receives a selection signal which includes a clocked pulse to turn on said selection transistor to output said pixel signal.

3. The device as in claim 1, wherein a drain of said output transistor is coupled to receive a drain supply voltage and a source of said output transistor is used to output said pixel signal.

4. The device as in claim 3, further comprising a power supply circuit for said output transistor and said drain of said reset transistor, said power supply circuit comprising first transistor and second transistor connected to each other and to receive said drain supply voltage, wherein said first transistor has a gate coupled to receive said reset control signal.

5. An integrated semiconductor device, comprising a radiation sensing array of a plurality of sensing pixels and an on-chip control circuit integrated to said radiation sensing array, each sensing pixel comprising:

a photodiode, responsive to radiation to produce charge and having a sensing node to output said charge;

an output transistor having a gate coupled to said sensing node to produce a pixel signal representing said charge; and

a reset transistor having a source formed from said sensing node, a gate coupled to receive a reset signal, and a drain coupled to a separate reset control signal which is pulsed on and off when said reset signal remains on to reset said sensing node and to erase a memory in said photodiode from a previous readout cycle.

6. The device as in claim 5, wherein said sensing pixels are arranged in columns along a X direction and rows along a Y direction, and wherein said on-chip control circuit includes:

a switching network coupled to said sensing array to receive pixel signals;

a plurality of computation circuits coupled to said switching network to compute inner products for at least X and Y centroids, said plurality of computation circuits having only passive elements to provide inner products of pixel signals from said switching network; and

a divider circuit coupled to said computation circuits to receive said inner products and compute said at least X and Y centroids.

7. The device as in claim 6, wherein said on-chip control circuit further comprises a block averaging circuit receiving said pixel signals and averaging said pixel signals over said columns.

8. The device as in claim 6, wherein said plurality of computation circuits include row-averaging banks and column-averaging banks.

9. The device as in claim 6, wherein said switching network is configured and coupled to said sensing array to connect a plurality of columns of pixels in parallel to respective computation circuit for parallel processing.

10. The device as in claim 6, wherein each computation circuit does not include an amplifier and includes capacitors that carry out centroid computations.

11. The device as in claim 5, further comprising a selection transistor coupled to said output transistor to receive said pixel signal and having a gate that receives a selection signal which includes a clocked pulse to turn on said selection transistor to output said pixel signal.

12. The device as in claim 5, wherein a drain of said output transistor is coupled to receive a drain supply voltage and a source of said output transistor is used to output said pixel signal.

13. The device as in claim 12, further comprising a power supply circuit for said output transistor and said drain of said reset transistor, said power supply circuit comprising first transistor and second transistor connected to each other and to receive said drain supply voltage, wherein said first transistor has a gate coupled to receive said reset control signal.

14. A method for sensing radiation, comprising:

causing an array of photodiodes to be formed in a sensing array for detecting radiation, where each photodiode is responsive to the radiation to produce charge and has a gate coupled to said sensing node to produce a pixel signal representing said charge;

causing a reset transistor to be formed adjacent to each photodiode to reset said photodiode after each readout, wherein said reset transistor has a source formed from said sensing node, a gate coupled to receive a reset signal, and a drain coupled to a separate reset control signal; and

during a period when said reset signal is pulsed to an on state, causing said reset control signal to be pulsed on and off to reset said sensing node and to erase a memory in said photodiode from a previous readout cycle.

15. A method for sensing radiation, comprising:

causing an array of photodiodes to be formed in a sensing array for detecting radiation, where each photodiode is responsive to the radiation to produce charge and has a gate coupled to said sensing node to produce a pixel signal representing said charge;

causing a reset transistor to be formed adjacent to each photodiode to reset said photodiode after each readout, wherein said reset transistor has a source formed from said sensing node, a gate coupled to receive a reset signal, and a drain coupled to a separate reset control signal;

during a period when said reset signal is pulsed to an on state, causing said reset control signal to be pulsed on and off to reset said sensing node and to erase a memory in said photodiode from a previous readout cycle; and

causing pixel signals from said sensing array to be processed on the chip to produce centroids for a selected block of photodiodes along two different directions.