High dynamic range low ripple RSSI for zero-IF or low-IF receivers

• US 6,721,548 B1
• Filed: 12/22/1999
• Issued: 04/13/2004
• Est. Priority Date: 12/22/1999
• Status: Expired due to Term

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Stroet, Petrus M., Mohindra, Rishi
• Primary Examiner(s): Tran, Sinh
• Assistant Examiner(s): Afshar, Kamran
• Application Number:
  US09/469,330
• Time in Patent Office: 1,574 Days
• Field of Search: 455/234.1, 455/250.1, 455/226.1, 455/226.2, 455/227, 455/324, 455/269, 455/273, 455/323, 455/313, 327/354, 327/355, 327/356, 327/357, 327/361, 375/322, 375/324
• US Class Current: 455/234.1
• CPC Class Codes: H04B 17/318 Received signal strength

Abstract

A received signal strength indicator operating at low intermediate of zero intermediate frequency is provided. The received signal strength indicator forms absolute values from an in-phase signal component and a quadrature signal component of a low or zero intermediate frequency signal that represents a received radio frequency signal. The absolute values are added. Logarithmic signal processing is performed either before absolute signal forming or after adding. Finally, low pass filtering is performed.

Claims

1. A method of determining a received signal strength indicator signal from an in-phase signal component and a quadrature signal component of a low intermediate frequency signal that represents a received radio frequency signal, said method comprising:

determining a first absolute value from said in-phase signal component;

determining a second absolute value from said quadrature signal component;

logarithmically processing said in-phase and quadrature signal components; and

summing said first and second absolute values;

wherein said logarithmically processing comprises multistage limiting of said in-phase and quadrature signal components, and summing said multistage limited in-phase and quadrature signal components.

2. A method as claimed in claim 1, wherein said logarithmically processing said in-phase and quadrature signal component is performed before determining said first and second absolute values.

3. A method as claimed in claim 1, wherein said logarithmically processing said in-phase and quadrature signal component is performed after summing said first and second absolute values.

4. A method as claimed in claim 1, wherein said received signal strength indicator signal is further determined by low pass filtering said summed first and second absolute values.

5. A method as claimed in claim 1, wherein said low intermediate frequency signal is a zero intermediate frequency signal.

6. A radio device comprising:

an antenna for receiving a radio frequency signal;

a quadrature down converter for producing a low intermediate frequency in-phase signal component and a low intermediate frequency quadrature signal component from said radio frequency signal;

a received signal strength indicator for producing a received signal strength indicator signal from said low intermediate frequency in-phase and quadrature signal components, said received signal strength indicator comprising a first absolute value former for deriving a first absolute signal from said in-phase signal component, a second absolute value former for deriving a second absolute signal from said quadrature signal component, and an adder for adding said first and second absolute signal,

wherein said received signal strength indicator further comprises a first logarithmic signal former for determining a first logarithmic signal from said in-phase signal component and a second logarithmic signal former for determining a second logarithmic signal from said quadrature signal component, said first absolute signal being said first logarithmic signal and said second absolute signal being said second logarithmic signal; and

wherein said first and second logarithmic signal formers comprise respective multistage limiters and respective adders for adding signals produced by said multistage limiters.

7. A radio device as claimed in claim 6, wherein said received signal strength indicator further comprises a low pass filter for low pass filtering said added first and second absolute signals.

8. A radio device as claimed in claim 6, wherein said low intermediate frequency signal is a zero intermediate frequency.

9. A received signal strength indicator for use in radio device with an antenna for receiving a radio frequency signal, a quadrature down converter for producing a low intermediate frequency in-phase signal component and a low intermediate frequency quadrature signal component from said radio frequency signal, and said received signal strength indicator for producing a received signal strength indicator signal from said low intermediate frequency in-phase and quadrature signal components, said received signal strength indicator comprising

a first absolute value former for deriving a first absolute signal from said in-phase signal component;

a second absolute value former for deriving a second absolute signal from said quadrature signal component; and

an adder for adding said first and second absolute signals;

wherein said received signal strength indicator further comprises a first logarithmic signal former for determining a first logarithmic signal from said in-phase signal component and a second logarithmic signal former for determining a second logarithmic signal from said quadrature signal component, said first absolute signal being said first logarithmic signal and said second absolute signal being said second logarithmic signal; and

wherein said first and second logarithmic signal formers comprise respective multistage limiters and respective adders for adding signals produced by said multistage limiters.

10. The received signal strength indicator as claimed in claim 9, wherein said low intermediate frequency signal is a zero intermediate frequency signal.

11. The received signal strength indicator of claim 9, wherein the multi-stage limiters each comprise a cascade of differential amplifiers.