Reprogrammable digital wireless communication device and method of operating same

• US 6,721,581 B1
• Filed: 05/05/2000
• Issued: 04/13/2004
• Est. Priority Date: 05/07/1999
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Infineon Technologies AG
• Inventors: Subramanian, Ravi
• Primary Examiner(s): Trost, William
• Assistant Examiner(s): RAMPURIA, SHARAD K
• Application Number:
  US09/565,687
• Time in Patent Office: 1,439 Days
• Field of Search: 455/550, 455/552, 455/557, 455/575, 455/87, 455/542, 455/323, 455/419, 375/219, 375/222, 375/220, 375/316
• US Class Current: 455/575.1
• CPC Class Codes: H04B 1/0003 Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00
• CPC Class Codes: H04B 1/005 adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges
• CPC Class Codes: H04B 1/406 with more than one transmission mode, e.g. analog and digital modes

Abstract

A digital wireless communication device comprises a software-programmable processor, a heterogeneous reconfigurable multiprocessing logic circuit, and a bus connecting the software-programmable processor and the heterogeneous reconfigurable multiprocessing logic circuit. The heterogeneous reconfigurable multiprocessing logic circuit comprises a set of heterogeneous signal processing kernels and a reconfigurable data router interconnecting the heterogeneous signal processing kernels. The software-programmable processor is selected from the group comprising: a digital signal processor and a central processing unit. The architecture provides the ability to reconfigure a single product platform for multiple standards, applications, services, and quality-of service, instead of developing multiple hardware platforms to establish the same collective functionality. The architecture also provides the ability to use software programming techniques to reduce product development time and achieve rapid and comprehensive product customization. The invention extends the performance efficiency of microprocessors and digital signal processors via the augmentation of data paths and control paths through a reconfigurable co-processing machine. The reconfigurability of the data path optimizes the performance of the data flow in the algorithms implemented on the processor.

Claims

1. A digital wireless communication device, comprising:

a radio-frequency (RF) subsystem;

an analog-to-digital converter for converting analog signals from said RF subsystem to digital signals;

a software-programmable processor;

a heterogeneous reconfigurable multiprocessor for processing said digital signals; and

a bus connecting said software-programmable processor and said heterogeneous reconfigurable multiprocessor.

2. The digital wireless communication device of claim 1 wherein the software-programmable processor is selected from the group comprising a digital signal processor and a central processing unit.

3. The digital wireless communication device of claim 1 wherein said software-programmable processor executes a set of software modules specifying a set of wireless communication applications, standards, and services to be implemented.

4. The digital wireless communication device of claim 1 wherein said heterogeneous reconfigurable multiprocessor comprises a plurality of programmable data processing kernels, each data processing kernel of said plurality of data processing kernels including a data sequencer, a local memory, and an arithmetic logic unit.

5. The digital wireless communication device of claim 4 wherein said plurality of programmable data processing kernels are programmed to implement a set of wireless communication applications, standards, and services.

6. A method of programming a digital wireless communication device to support a wireless communication application, standard, and service, said method comprising the steps of:

selecting a set of parameters and values required to implement a specified wireless communication application, standard, and service;

downloading said set of parameters and values to a digital wireless communication device including a heterogeneous reconfigurable multiprocessor with a plurality of re-programmable data processing kernels; and

operating said plurality of re-programmable data processing kernels in accordance with said set of parameter and values to support said specified communication application, standard, and service.

7. The method of claim 6 wherein said selecting step includes the step of selecting a set of parameters and values from the group comprising:

a country of operation, a frequency band, and a data rate.

8. The method of claim 6 wherein said downloading step includes the step of downloading said set of parameters over a wireless communication channel.

9. The method of claim 6 wherein said downloading step includes the step of downloading said set of parameters at the time of manufacture.

10. The method of claim 6 wherein said downloading step includes the step of downloading said set of parameters at a point of sale.

11. A mobile digital wireless communication device, comprising:

a radio-frequency (RE) subsystem to digital signals;

an analog-to-digital converter for converting analog signals from said RF subsystem to digital signals;

a software-programmable processor;

a heterogeneous reconfigurable multiprocessor for processing said digital signals;

a memory, including;

executive code that is executable on the software-programmable processor; and

a set of platform-dependent software modules specifying a set of wireless communication applications, standards, and services, wherein a subset of the software modules is executable on the heterogeneous reconfigurable multiprocessor; and

a bus connecting said analog-to-digital converter, software-programmable processor, and heterogeneous reconfigurable multiprocessor.