I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures

• US 6,721,830 B2
• Filed: 11/26/2002
• Issued: 04/13/2004
• Est. Priority Date: 12/20/1996
• Status: Expired due to Term

• Current Assignee: Scientia Sol Mentis AG (PACT XPP Schweiz AG)
• Original Assignee: Pact XPP Technologies, AG
• Inventors: Vorbach, Martin, Münch, Robert
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US10/304,252
• Publication Number:
  US 20030097513A1
• Time in Patent Office: 504 Days
• Field of Search: 710/100, 710/300, 710/8, 710/72, 710/305, 712/11, 712/14, 712/18, 716/17, 716/16, 326/38, 326/39, 326/41, 439/68
• US Class Current: 710/100
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (for cascading).

Claims

1. A method of managing external terminals of a module having a multidimensional cell structure, at least one of the external terminals being configured to communicatively couple to at least one corresponding terminal of at least one external module, an internal bus system communicatively coupled to the cell structure and to the external terminals of the module, the method comprising:

assigning a unit to at least one of the internal bus system and a group of lines;

generating protocols for at least one of the external module and an external bus, the protocols being generated by the unit;

generating an address for the at least one of the external module and the external bus, the address being generated by the unit; and

controlling a synchronization of the multidimensional cell structure with at least one of the external module and the external bus, the synchronization being controlled by the unit.

2. The method according to claim 1, further comprising:

programming an address generator, the unit including the address generator.

3. The method according to claim 2, further comprising:

setting a counter increment of the address generator.

4. The method according to claim 2, further comprising:

setting a counter direction of the address generator.

5. The method according to claim 2, further comprising:

setting a starting value of an address counter.

6. The method according to claim 1, further comprising:

exchanging information between the unit and a second unit.

7. The method according to claim 1, further comprising:

routing internal lines to an indexed unit; and

combining the internal lines to form a bus having a pre-determined bit width.

8. The method according to claim 7, wherein the bus is unidirectional.

9. The method according to claim 8, wherein the bus includes a read bus.

10. The method according to claim 8, wherein the bus includes a write bus.

11. The method according to claim 10, wherein the bus is bidirectional.

12. The method according to claim 1, further comprising:

controlling the unit by a higher-level control unit;

managing the unit by the higher-level control unit; and

programming the unit by the higher-level control unit.

13. The method according to claim 1, wherein the multidimensional cell structure at least one of controls, programs, and manages the unit.

14. The method according to claim 1, wherein the unit includes an external unit, and the unit is configured to control a plurality of subordinate external units, each having a type that is the same as a type of the unit.

15. The method according to claim 14, further comprising:

requesting control over the external bus by one of the plurality of subordinate external units;

transferring control of the external bus to the one of the plurality of subordinate external units after the request for control; and

after transferring control, operating the unit over the external bus as a subordinate unit to the one of the plurality of subordinate external units, the unit being operated as a subordinate unit of the external bus.

16. The method according to claim 1, wherein the unit is configured to request control over the external bus if required and if the unit is connected to the external bus as a subordinate unit.

17. A unit for managing terminals of at least one external module, comprising:

a programmable multidimensional cell structure;

an internal bus system communicatively coupled to the cell structure and to the terminals of the external module;

a protocol arrangement to generate protocols for at least one of the external module and an external bus;

an address arrangement to generate addresses for the external module; and

a synchronization arrangement to synchronize the multidimensional cell structure with at least one of the external module and the external bus;

wherein the unit is assigned to at least one of an internal bus system and a group of lines.

18. The unit according to claim 17, further comprising:

at least one hold circuit assigned to at least a portion of at least one of input data and output data.

19. The unit according to claim 17, wherein the multidimensional cell structure includes a terminal for a module configuration.

20. An apparatus to manage terminals of at least one external module having a programmable multidimensional cell structure, comprising:

an internal bus system including a plurality of internal buses; and

an arrangement configured to connect a selected internal bus of the plurality of internal busses to a selected external bus of a plurality of external busses;

wherein a number of the plurality of external buses is smaller than a number of the plurality of internal buses.

21. An apparatus to manage access to terminals of at least one external module having a programmable multidimensional cell structure, comprising:

a plurality of internal buses;

a plurality of external buses; and

a cache arrangement communicatively arranged between at least one of the internal buses and at least one of the external buses, the cache arrangement configured to cache data to be requested via the external buses and configured to provide a connection to the external buses, the connection being provided only for data that is one of not cached and not cachable.

22. An arrangement, comprising:

a processor including a plurality of cells configurable with regard to function and interconnections;

a memory;

a cache-memory management arrangement; and

an internal global bus system communicatively coupled to the cache-memory management arrangement, the plurality of cells being connectable via the internal global bus system.

23. The arrangement according to claim 22, wherein the processor includes a co-processor.

24. A unit to manage terminals of at least one external module, comprising:

a programmable multidimensional cell structure;

an internal bus system communicatively coupled to the multidimensional cell structure;

a control arrangement to control a synchronization of the multidimensional cell structure with at least one of the external module and an external bus; and

an address arrangement to generate addresses for the external module;

wherein the unit is assigned to at least one of the internal bus system and a group of lines.

25. A unit to manage terminals of at least one external module having a programmable multidimensional cell structure, the unit comprising

a plurality of internal buses;

a first multiplexer arrangement configured to permit one of the plurality of internal buses to be selected for connection to at least one of;

the terminals of the external module, and

a plurality of external terminals; and

a second multiplexer arrangement configured to permit one of the terminals of the external module to be selected for connection to one of the plurality of internal buses.

26. An arrangement, comprising:

a processor including a plurality of cells configurable with regard to function and interconnections;

at least one of a memory and a peripheral;

an address arrangement configured to address the least one of the memory and the peripheral; and

an internal global bus system communicatively coupled to the address arrangement, the plurality of cells being connectable via the internal global bus system.

27. The arrangement according to claim 26, wherein the processor includes a co-processor.

28. The arrangement according to claim 27, further comprising:

hold circuits assigned to at least a portion of at least one of incoming data and outgoing data.

29. The arrangement according to claim 26, further comprising:

a terminal for a module configuration by the cell structure.