Graphics display system with unified memory architecture

• US 6,721,837 B2
• Filed: 12/17/2002
• Issued: 04/13/2004
• Est. Priority Date: 11/09/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: MacInnis, Alexander G., Tang, Chengfuh Jeffrey, Kranawetter, Greg A., Patterson, James T., Xie, Xiaodong
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US10/322,059
• Publication Number:
  US 20030158987A1
• Time in Patent Office: 483 Days
• Field of Search: 710/240, 710/241, 710/244, 710/107, 710/116, 710/40, 710/41, 711/151, 711/100, 711/147, 711/148, 345/530, 345/156
• US Class Current: 710/244
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 9/00 Image coding bandwidth or redundancy reduction for static pictures H04N1/41; coding or decoding of static colour picture signals H04N1/64; methods or arrangements for coding, decoding, compressing or decompressing digital video signals H04N19/00
• CPC Class Codes: G06T 9/007 Transform coding, e.g. discrete cosine transform
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 2340/10 Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 2360/126 The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
• CPC Class Codes: G09G 2360/128 Frame memory using a Synchronous Dynamic RAM [SDRAM]
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/02 : characterised by the way in which colour is displayed details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 5/024 : using colour registers, e.g. to control background, foreground, surface filling G09G5/06 takes precedence
• CPC Class Codes: G09G 5/026 : Control of mixing and/or overlay of colours in general G09G5/022 and G09G5/024 take precedence
• CPC Class Codes: G09G 5/06 : using colour palettes, e.g. look-up tables
• CPC Class Codes: G09G 5/12 : Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• CPC Class Codes: G09G 5/14 : Display of multiple viewports
• CPC Class Codes: G09G 5/28 : for enhancement of character form, e.g. smoothing
• CPC Class Codes: G09G 5/346 : for systems having a bit-mapped display memory
• CPC Class Codes: G09G 5/36 : characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
• CPC Class Codes: G09G 5/363 : Graphics controllers
• CPC Class Codes: H04N 11/143 : Encoding means therefor H04N11/16 takes precedence
• CPC Class Codes: H04N 11/20 : Conversion of the manner in which the individual colour picture signal components are combined, e.g. conversion of colour television standards
• CPC Class Codes: H04N 19/42 : characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 : characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/436 : using parallelised computational arrangements
• CPC Class Codes: H04N 19/44 : Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/59 : involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution
• CPC Class Codes: H04N 19/61 : in combination with predictive coding
• CPC Class Codes: H04N 21/42204 : User interfaces specially adapted for controlling a client device through a remote control device; Remote control devices therefor constructive details of casings for the remote control device H01H9/0235; user interfaces for controlling a tuning device of a television receiver through a remote control H03J9/00; remote control of peripheral devices connected to a television receiver through the remote control device of the television receiver H04B1/205
• CPC Class Codes: H04N 21/426 : Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/42653 : for processing graphics
• CPC Class Codes: H04N 21/4305 : Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/4316 : for displaying supplemental content in a region of the screen, e.g. an advertisement in a separate window
• CPC Class Codes: H04N 21/434 : Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream demultiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/440263 : by altering the spatial resolution, e.g. for displaying on a connected PDA
• CPC Class Codes: H04N 21/4438 : Window management, e.g. event handling following interaction with the user interface
• CPC Class Codes: H04N 21/47 : End-user applications
• CPC Class Codes: H04N 5/04 : Synchronising for television systems using pulse code modulation H04N7/56
• CPC Class Codes: H04N 5/126 : whereby the synchronisation signal indirectly commands a frequency generator
• CPC Class Codes: H04N 5/14 : Picture signal circuitry for video frequency region cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00
• CPC Class Codes: H04N 5/44504 : Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits
• CPC Class Codes: H04N 5/45 : Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen
• CPC Class Codes: H04N 5/46 : for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27
• CPC Class Codes: H04N 7/0122 : the input and the output signals having different aspect ratios
• CPC Class Codes: H04N 7/0135 : involving interpolation processes interpolation-based image scaling G06T3/4007; interpolation for video coding H04N19/587, H04N19/59
• CPC Class Codes: H04N 9/45 : Generation or recovery of colour sub-carriers
• CPC Class Codes: H04N 9/641 : Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence
• CPC Class Codes: H04N 9/642 : Multi-standard receivers

Abstract

A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.

Claims

1. A method of arbitrating memory requests to access a memory from a plurality of different devices having different priorities, the memory being shared by the devices, the method comprising:

receiving a memory request from at least one device;

serving the memory request by allowing an access to the memory by the at least one device; and

enforcing a predetermined minimum interval between the access and a subsequent access to the memory by the at least one device, thereby precluding the at least one device from accessing the memory at its priority when another memory request is received from the at least one device during the predetermined minimum interval.

2. The method according to claim 1, wherein the at least one device comprises a high priority device.

3. The method according to claim 1, wherein the at least one device comprises at least one selected from a group consisting of a CPU, a display engine, a graphics accelerator and a window controller.

4. The method according to claim 1, wherein enforcing a predetermined minimum interval comprises:

running a counter associated with the at least one device for the predetermined minimum interval; and

precluding the at least one device from accessing the memory at its priority while the associated counter is running.

5. The method according to claim 4, wherein the at least one device comprises a high priority device, and wherein receiving a memory request comprises receiving a high priority service request in association with the counter.

6. The method according to claim 4, further comprising programming the associated counter to modify the predetermined interval.

7. The method according to claim 4, further comprising servicing the memory requests from the at least one device in a round robin manner while the associated counter is running.

8. The method according to claim 1, wherein the memory requests comprise low priority service requests that are serviced when higher priority requests are not being serviced.

9. The method according to claim 8, wherein the low priority service requests are serviced in a round robin manner.

10. The method according to claim 8, wherein the low priority service requests are serviced in a pre-determined order.

11. The method according to claim 8, wherein the low priority service requests are serviced using pre-determined time slots.

12. The method according to claim 11, wherein if a service request does not use an entire time slot, then at least part of that time slot is made available for other service requests to use.

13. The method according to claim 1, wherein the devices comprise low priority devices that are serviced when higher priority devices are not being serviced.

14. The method according to claim 13, wherein the low priority devices are serviced in a round robin manner.

15. The method according to claim 13, wherein the low priority devices are serviced in a pre-determined order.

16. The method according to claim 13, wherein the low priority devices are serviced using pre-determined time slots.

17. The method according to claim 16, wherein if a device does not use an entire time slot, then at least part of that time slot is made available for other devices to use.

18. A method of arbitrating memory requests to access a memory from a plurality of different devices having different priorities, the memory being shared by the devices, the method comprising:

receiving at least one memory request from at least one device;

serving the at least one memory request by allowing at least one access to the memory by the at least one device; and

enforcing a predetermined minimum interval between the at least one access and a subsequent access to the memory by the at least one device, thereby precluding the at least one device from accessing the memory at its priority when a memory request is received from the at least one device during the predetermined minimum interval.

19. A method of arbitrating memory requests to access a memory from a plurality of different devices having different priorities, the memory being shared by the devices, the method comprising:

receiving a memory request from at least one device;

serving the memory request by allowing at least one access to the memory by the at least one device; and

enforcing a predetermined minimum interval between the at least one access and subsequent accesses to the memory by the at least one device, thereby precluding the at least one device from accessing the memory at its priority when another memory request is received from the at least one device during the predetermined minimum interval.

20. A method of arbitrating memory requests to access a memory from a plurality of different devices having different priorities, the memory being shared by the devices, the method comprising:

receiving a plurality of memory requests from at least one device;

serving the plurality of memory requests by allowing at least one access to the memory by the at least one device; and

enforcing a predetermined minimum interval between the at least one access and subsequent accesses to the memory by the at least one device, thereby precluding the at least one device from accessing the memory at its priority when one of the plurality of memory requests is received from the at least one device during the predetermined minimum interval.

21. A method for arbitrating memory access in an apparatus having a memory request arbiter that arbitrates access to a memory for different devices having different priorities, at least one counter coupled to the memory request arbiter and associated with at least a first device of a plurality of devices, the method comprising:

providing a time-out period by the counter to the first device; and

precluding access by the first device to the memory at its priority in response to the time-out period.

22. The method according to claim 21, wherein the first device comprises a CPU.

23. The method according to claim 21, wherein the first device comprises a graphics device.

24. The method according to claim 23, wherein the graphics device comprises at least one selected from a group consisting of a graphics accelerator and a display engine.

25. The method according to claim 21, wherein the first device comprises a window controller.

26. The method according to claim 21, further comprising arbitrating between memory requests from at least two devices.

27. The method according to claim 26, wherein at least one of the at least two devices does not have a determinable periodic behavior.

28. The method according to claim 27, wherein at least one of the at least two devices has a determinable periodic behavior.

29. The method according to claim 21, further comprising programming the timer.

30. The method according to claim 21, further comprising round-robin scheduling memory requests from at least two devices.

31. The method according to claim 30, wherein the round-robin scheduled memory requests comprise memory requests from low priority devices.

32. The method according to claim 30, wherein the round-robin scheduled memory requests comprise memory requests from at least one high priority device, during the time-out period associated with the at least one high priority device.