Flash memory architecture implementing simultaneously programmable multiple flash memory banks that are host compatible

• US 6,721,843 B1
• Filed: 07/07/2000
• Issued: 04/13/2004
• Est. Priority Date: 07/07/2000
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Lexar Media Incorporated (Micron Technology, Inc.)
• Inventors: Estakhri, Petro
• Primary Examiner(s): Bragdon, Reginald G.
• Assistant Examiner(s): Vital, Pierre M.
• Application Number:
  US09/611,676
• Time in Patent Office: 1,376 Days
• Field of Search: 711/5, 711/103-104, 711/202, 711/203, 711/206, 365/185.09, 365/185.11, 365/230.03, 365/230.08, 709/228
• US Class Current: 711/103
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A Flash Memory Unit comprises a plurality of memory banks capable of simultaneously programming a plurality of pages into a plurality of data blocks within the respective memory banks. On start up, the Flash Memory System sends a signal to a Host. If the Host fails to respond, the Flash Memory Unit determines that the Host is a standard Host and stores data one page at a time. If the Host responds with a proper signal, the Flash Memory Unit determines that the Host is a high performance Host and stores multiple pages of data simultaneously. The high performance Host is configured to select identical LBA offsets from a plurality of Virtual Logical Blocks of User Data, and send the data defined by these Logical Block Addresses to the Flash Memory Unit for storage. The plurality of Logical Blocks of data are respectively transmitted to a plurality of RAM Data Registers, and simultaneously programmed into their respective memory banks. In sequential steps of programming, data defined by consecutive Logical Block Addresses are stored in Physical Pages defined by consecutive Physical Block Addresses. Data stored by a high performance Host is therefore retrievable by a standard Host.

Claims

1. A flash memory system comprising a plurality of separate and independently addressable memory banks, each memory bank comprising:

a. a plurality of independently addressable and independently programmable non-volatile data storage areas;

b. a primary RAM data register; and

c. a vendor unique value, including means for loading the vendor unique value into a handshake data packet upon start up,

wherein the flash memory system is configured to selectively operate in a first mode of data storage and in a second mode of data storage in response to the vendor unique value, the first mode of data storage being a default mode, wherein a single programming cycle according to the first mode of data storage comprises a storage of data into a single RAM data register for programming into a single page.

2. The flash memory system according to claim 1 further comprising a controller with a host interface circuit, a RAM data buffer and a memory interface circuit, the RAM data buffer being operatively coupled to the host interface circuit and to the memory interface circuit, the memory interface circuit being operatively coupled to the primary RAM data register in each of the plurality of memory banks by means of a data bus, wherein the controller is capable of controlling a programming of data into the plurality of data storage areas distributed among the plurality of memory banks through the primary RAM data register associated with the respective plurality of memory banks.

3. The flash memory system according to claim 2 wherein the data storage areas within the plurality of memory banks include a plurality of physical data blocks, each physical data block being comprised of a plurality of pages.

4. The flash memory system according to claim 3 wherein the single programming cycle according to the second mode of data storage comprises the storage of data from the RAM data buffer into a plurality of RAM data registers, wherein the plurality of RAM data registers simultaneously program data into a respective plurality of pages.

5. The flash memory system according to claim 4 further comprising:

a. a host; and

b. means for transmitting the handshake data packet to the host upon start up.

6. The flash memory system according to claim 5 wherein the controller is configured to store incoming user data according to the first mode of data storage when no responsive handshake is received from the host.

7. The flash memory system according to claim 6, wherein the controller is configured to store incoming user data according to the second mode of data storage when a responsive handshake is received from the host.

8. The flash memory system according to claim 7 wherein a RAM data register comprises sufficient memory to program a physical page.

9. The flash memory system according to claim 7 further comprising means for selecting a plurality of logical blocks of incoming data to be programmed into separate pages within the flash memory system during a cycle of operation.

10. The flash memory system according to claim 9 wherein means for selecting the plurality of logical blocks is resident within the host.

11. The flash memory system according to claim 10 wherein the host is a digital camera.

12. The flash memory system according to claim 9 wherein means for selecting the plurality of logical blocks is resident within the flash memory system.

13. The flash memory system according to claim 12 wherein the RAM data buffer comprises sufficient memory to store an entire file of incoming user data.

14. The flash memory system according to claim 9, wherein each memory bank further comprising an auxiliary RAM data register, wherein a first auxiliary RAM data buffer within a first memory bank is capable of programming data into data storage areas within the first memory bank, and a second auxiliary RAM data register is capable of programming data into data storage areas within a second memory bank.

15. A method of programming incoming data into a multibank flash memory system comprising a vendor unique value, a controller operatively coupled to a memory system, the controller comprising a RAM data buffer operatively coupled to a memory interface circuit, the flash memory system comprising a plurality of separate and individually addressable memory banks, each memory bank comprising a primary RAM data register and a plurality of individually addressable and individually programmable physical data blocks, each physical data block comprising a plurality of individually addressable and individually programmable pages, the method comprising the steps of:

a. generating a handshake data packet;

b. loading the vendor unique value within the flash memory system into the handshake data packet;

c. sending the handshake data packet from the flash memory system to a host;

d. defaulting to a first data storage configuration; and

e. programming incoming data into the flash memory system according to a first data storage method, wherein the first data storage method comprises the step of programming one page of user data per programming cycle,

wherein the flash memory system is configured to selectively operate in a first mode of data storage and in a second mode of data storage in response to the vendor unique value, the first mode of data storage being a default mode.

16. The method according to claim 15 further comprising the steps of:

a. sending a reply handshake from the host to the flash memory system;

b. configuring the flash memory system according to a second data storage configuration; and

c. programming incoming data into the flash memory system according to the second data storage method, wherein the second data storage method comprises the step of simultaneously programming a plurality of pages of data into multiple memory banks on each programming cycle.

17. The method according to claim 16 wherein the step of programming incoming data into the flash memory system according to the second data storage method further comprises the steps of:

a. loading a first initial logical block of data defined by a first VLBA a first primary RAM data register within a first memory bank;

b. loading a second initial logical block of data defined by a second VLBA into a second primary RAM data register within a second memory bank; and

c. simultaneously programming;

i. the first initial logical block of data within the first primary RAM data register into a first initial page of a first physical data block within the first memory bank, and

ii. the second initial logical block of data within the second primary RAM data register into a second initial page of a second physical data block within the second memory bank.

18. The method according to claim 17 further comprising the steps of:

a. loading a first subsequent logical block of data defined by the first VLBA into the first primary RAM data register within the first memory bank;

b. loading a second subsequent logical block of data defined by a second VLBA into the second primary RAM data register within the second memory bank; and

c. simultaneously programming;

i. the first subsequent logical block of data within the first primary RAM data register into a first subsequent page of the first physical data block; and

ii. the second subsequent logical block of data within the second primary RAM data register into a second subsequent page of the second physical data block.

19. The method according to claim 18 wherein:

a. the first initial logical block and the first subsequent logical block are defined by consecutive logical block addresses within the first virtual logical block;

b. the second initial logical block and the second subsequent logical block are defined by consecutive logical block addresses within the second virtual logical block;

c. the step of loading the first subsequent logical block sequentially follows the step of loading the first initial logical block data into the first primary RAM data register;

d. the step of loading the second subsequent logical block sequentially follows the step of loading the second initial logical block of data into the second primary RAM data register;

e. the first initial page and the first subsequent page are defined by consecutive physical block addresses within the first physical data block; and

f. the second initial page of the second subsequent page are defined by consecutive physical block addresses within the second physical data block.

20. The method according to claim 19 wherein each of the plurality of physical data blocks within the plurality of memory banks of the flash memory system comprises an identical number of pages which are addressed according to an identical page addressing scheme.

21. The method according to claim 20 wherein the first initial page within the first physical data block and the second initial page within the second physical data block are defined according to a same page address.

22. The method according to claim 21 wherein each memory bank comprises an identical number of physical data blocks which are addressed according to an identical block addressing scheme.

23. The method according to claim 22 wherein the first physical data block and the second physical data block are defined according to a same physical block address.

24. The method according to claim 23 wherein an address of the first memory bank and an address of the second memory bank are consecutive addresses.

25. The method according to claim 24 wherein each of the plurality of separate and separately addressable memory banks individually comprise a second auxiliary RAM data register, the method further comprising the steps of:

a. loading the first subsequent logical block of data within the first virtual logical block into a first auxiliary RAM data register within the first memory bank;

b. loading the second subsequent logical block of data within the second virtual logical block into the second auxiliary RAM data register within the second memory bank; and

c. simultaneously programming;

i. the first subsequent logical block of data within the first auxiliary RAM data register into a first subsequent page within the first physical data block; and

ii. the second subsequent logical block of data within the second auxiliary RAM data register into a second subsequent page within the second physical data block.

26. The method according to claim 25 wherein

a. the first initial logical block and the first subsequent logical block are consecutively addressed within the first virtual logical block addresses;

b. the second initial logical block and the second subsequent logical block are consecutively addressed within the second virtual logical block addresses;

c. the step of loading a first initial logical block and the step of loading a first subsequent logical block comprise sequential steps of loading data into a plurality of RAM data registers of the first memory bank;

d. the step of loading the second initial logical block and the step of loading the second subsequent logical block comprise sequential steps of loading data into a plurality of RAM data registers of the second memory bank;

e. the first initial page and the first subsequent page are consecutively addressed within the first physical data block; and

f. the second initial page and the second subsequent page are consecutively addressed within the second physical data block.

27. The method according to claim 20 wherein the step of programming incoming data into the flash memory system according to the first data storage method comprises sequential steps of:

a. programming data defined by a first logical block address into a first page of a physical data block; and

b. programming data defined by a second logical block address into a second page of the physical data block,

wherein the first logical block address and the second logical block address are defined by consecutive addresses within a same virtual logical block address, and wherein the first page and the second page are defined by consecutive physical block addresses within the same physical data block.

28. A method of programming a flash memory system with incoming data from a host, comprising the steps of:

a. operatively coupling the flash memory system to a host; and

b. examining a handshake data packet sent by the flash memory system,

wherein the flash memory system is configured to selectively operate in a first mode of data storage and in a second mode of data storage in response to the vendor unique value, the first mode of data storage being a default, wherein the method further comprises the steps of configuring the host to a standard mode of operation and storing data within the flash memory system according to the standard mode of operation when the handshake data packet lacks a vendor unique value.

29. The method according to claim 28, wherein the method further comprises the steps of configuring the host to a high-performance mode of operation and storing data within the flash memory system according to the high-performance mode of operation when the handshake data packet comprises the vendor unique value.

30. The method according to claim 29 wherein the step of storing data within the flash memory system according to the high-performance mode of operation comprises the steps of:

a. loading a first initial logical block of data defined by a first VLBA into a first primary RAM data register within a first memory bank;

b. loading a second initial logical block of data defined by a second VLBA into a second primary RAM data register within a second memory bank; and

c. simultaneously programming;

i. the first initial logical block of data within the first primary RAM data register into a first initial page of a first physical data block within the first memory bank, and

ii. the second initial logical block of data within the second primary RAM data register into a second initial page of a second physical data block within the second memory bank.

31. The method according to claim 30 further comprising the steps of:

a. loading a first subsequent logical block of data defined by the first VLBA into the first primary RAM data register within the first memory bank;

b. loading a second subsequent logical block of data defined by a second VLBA into the second primary RAM data register within the second memory bank; and

c. simultaneously programming;

i. the first subsequent logical block of data within the first primary RAM data register into a first subsequent page of the first physical data block; and

ii. the second subsequent logical block of data within the second primary RAM data register into a second subsequent page of the second physical data block.

32. The method according to claim 31 wherein

a. the first initial logical block and the first subsequent logical block are defined by consecutive logical block addresses within the first virtual logical block;

b. the second initial logical block and the second subsequent logical block are defined by consecutive logical block addresses within the second virtual logical block;

c. the step of loading the first subsequent logical block sequentially follows the step of loading the first initial logical block data into the first primary RAM data register;

d. the step of loading the second subsequent logical block sequentially follows the step of loading the second initial logical block of data into the second primary RAM data register;

e. the first initial page and the first subsequent page are defined according to consecutive PBA'"'"'s within the first physical data block; and

f. the second initial page of the second subsequent page are defined according to consecutive PBA'"'"'s within the second physical data block.

33. The method according to claim 32 wherein each of the plurality of physical data blocks within the plurality of memory banks of the flash memory system comprises an identical number of pages which are addressed according to an identical page addressing scheme.

34. The method according to claim 33 wherein the first initial page within the first physical data block and the second initial page within the second physical data block are defined according to a same page address.

35. The method according to claim 34 wherein each memory bank comprises an identical number of physical data blocks which are addressed according to an identical block addressing scheme.

36. The method according to claim 35 wherein the first physical data block and the second physical data block are defined according to a same physical block address.

37. The method according to claim 28 wherein the step of storing data within a flash memory system according to the standard mode of operation comprises the steps of:

a. programming the data from a first logical block address into a first page of a physical data block; and

b. programming the data from a second logical block address into a second page of the physical data block,

wherein the first logical block address and the second logical block address are consecutive addresses within the same virtual logical block, and wherein the first page and the second page are defined by consecutive physical block addresses.

38. A flash memory system comprising:

a. a plurality of separate and independently addressable memory banks;

b. a primary RAM data register;

c. a vendor unique value, including means for loading the vendor unique value into a handshake data packet upon start up and means for examining the handshake data packet sent by the flash memory system;

d. means for simultaneously storing a plurality of data storage areas in an interleaved manner in the plurality of memory banks from the primary RAM data register in response to a predetermined vendor unique value, such that programming time is reduced; and

e. means for storing data sequentially in the memory banks in a non-interleaved manner in an absence of the predetermined vendor unique value.

39. A flash memory system comprising:

a. a plurality of separate and independently addressable memory banks;

b. a primary RAM data register;

c. a vendor unique value, including means for loading the vendor unique value into a handshake data packet upon start up and means for examining the handshake data packet sent by the flash memory system; and

d. means for storing data sequentially in the memory banks in a non-interleaved manner in an absence of a predetermined vendor unique value,

wherein the flash memory system is configured to simultaneously program a plurality of pages of data into the plurality of memory banks for a host that is capable of high performance flash memory operation.