System for executing computer program using a configurable functional unit, included in a processor, for executing configurable instructions having an effect that are redefined at run-time

• US 6,721,884 B1
• Filed: 02/11/2000
• Issued: 04/13/2004
• Est. Priority Date: 02/15/1999
• Status: Expired due to Term

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: De Oliveira Kastrup Pereira, Bernardo, Bink, Adrianus J., Hoogerbrugge, Jan
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): DU, THUAN N
• Application Number:
  US09/501,642
• Time in Patent Office: 1,523 Days
• Field of Search: 713/1, 713/2, 713/100, 709/101, 712/10, 712/11, 712/12, 712/14, 712/15
• US Class Current: 713/2
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3897 with adaptable data path

Abstract

A processor contains a configurable functional unit that is capable of executing reconfigurable instructions, whose effect can be redefined at run-time by loading a configuration program. Reconfigurable instructions are selected in combinations of more than one different reconfigurable instruction. A respective configuration program is generated for each combination of instructions. Each time when an instruction from one of the combinations is needed during execution and the configurable functional unit is not configured with the configuration program for that combination, the configuration program for all of the instructions of that combination into the configurable functional unit. The reconfigurable instruction selects which instruction of the combination is executed.

Claims

1. A method of executing a computer program with a processor including a configurable functional unit capable of executing configurable instructions having an effect that are redefined at run-time by a loading of a configuration program, the method comprising the steps of:

selecting a plurality of combinations of configurable instructions;

generating a respective configuration program for each combination of configurable instructions;

executing the computer program; and

each time when an instruction from one of the combinations of configurable instructions is needed during execution and the configurable functional unit is not configured with the respective configuration program for that combination of configurable instructions, triggering the configuration functional unit to load the respective configuration program for all of the configurable instructions of that combination into the configurable functional unit.

2. The method according to claim 1, wherein the step of generating the configuration programs includes cross-minimizing hardware resource use for different instructions in at least one of the configuration programs.

3. The method according to claim 2, wherein hardware resource use for selecting different instructions from the combination during program execution and for processing operand data according to the different instructions is cross-minimized.

4. The method according to claim 2, wherein the configurable functional unit contains a cross-point switch between an input for operand data and connection lines that connect respective outputs of the cross-point switch to different logical combination circuits, the cross-point switch being controlled by the configuration program, wherein programming of the connections in the cross-point switch is used to cross-minimize hardware resource use in the configurable functional unit.

5. The method according to claim 4, wherein at least part of bits for selecting the configurable instruction from the combination are applied to the cross-point switch interchangeably with the operand data.

6. A processor, comprising:

a configurable functional unit for executing configurable instructions having an effect that is redefined at run-time by loading a configuration program, said configurable functional unit including a load triggering circuit for triggering loading of the configuration program when that configuration program is not yet loaded when needed for executing a configurable instruction,

wherein the configuration program defines the effect of at least two combined configurable instructions, said load triggering circuit triggering loading of the configuration program for all of the combined configurable instructions when at least one of the combined configurable instructions is needed.

7. The processor according to claim 6,

wherein said configurable functional unit further includes

an instruction selection input for selecting an instruction from the combination,

an operand data input,

combination logic, and

a result output;

wherein the operand data input and the instruction selection inputs are both coupled to the result output via the combination logic; and

wherein the instruction selection input and operand data input are interchangeable.

8. The processor according to claim 7, wherein said configurable functional unit includes a cross-point switch between the combination logic and the operand data input and the instruction selection inputs, said cross-point switch interchangeably connecting the instruction selection input and operand data input to the combination logic functionally interchangeably.

9. The processor according to claim 6, wherein said configurable functional unit includes a programmable logic device that imparts a substantially fixed operand-result delay, irrespective of which one of a plurality of classes of possible connections that implement the configurable instructions of the combinations are connected under control of the configuration program.

10. The processor of according to claim 6,

wherein said configurable functional unit further includes a cross-point switch operable to receive a configurable instruction selection code indicative of a first configurable instruction included within the at least two combined configurable instructions.

11. The processor of according to claim 10,

wherein said configurable functional unit executes the first configurable instruction subsequent to a loading of the at least two combined configurable instructions within said configurable functional unit and subsequent to a reception of the configurable instruction selection code by said cross-point switch.

12. The processor according to claim 6,

wherein said triggering circuit is operable to receive a first portion of the configurable instruction selection code, the first portion being indicative of the at least two combined configurable instructions.

13. The processor according to claim 12,

wherein said configurable functional unit further includes a cross-point switch operable to be reprogrammed;

and

wherein said triggering circuit reprograms said cross-point switch in accordance with the at least two combined configurable instructions in response to an exclusion by said triggering circuit of the at least two combined configurable instructions as indicated by the first portion of the configurable instruction selection code.

14. The processor of according to claim 13,

wherein said cross-point switch is further operable to receive a second portion of the configurable instruction selection code, the second portion being indicative of a first configurable instruction included within the at least two combined configurable instructions.

15. The processor of according to claim 14,

wherein said configurable functional unit executes the first configurable instruction subsequent to a reprogramming of said cross-point switch in accordance with the at least two combined configurable instructions and subsequent to a reception of the second portion of the configurable instruction selection code by said cross-point switch.

16. The processor according to claim 12,

wherein said configurable functional unit further includes at least one logic block operable to be reprogrammed;

and

wherein said triggering circuit reprograms said at least one logic-block in accordance with the at least two combined configurable instructions in response to an exclusion by said triggering circuit of the at least two combined configurable instructions as indicated by the first portion of the configurable instruction selection code.

17. The processor of according to claim 16,

wherein configurable functional unit further includes a said cross-point switch operable to receive a second portion of the configurable instruction selection code, the second portion being indicative of a first configurable instruction included within the at least two combined configurable instructions.

18. The processor of according to claim 17,

wherein said configurable functional unit executes the first configurable instruction subsequent to a reprogramming of said at least two logic-blocks in accordance with the at least two combined configurable instructions and subsequent to a reception of the second portion of the configurable instruction selection code by said cross-point switch.

19. The processor according to claim 6,

wherein said configurable functional unit further includes means for executing a first configurable instruction included within the at least two combined configurable instructions subsequent to a loading of the at least two combined configurable instructions within said configurable functional unit.

20. A computer program product for generating machine code for a processor including configurable processing unit, the machine code including a plurality of configurable instructions, the computer program product being arranged to select a combination of configurable instructions for combined loading into the configurable processing unit, said computer program product comprising:

computer program code for determining for each of a number of configurable instructions which of bits of a plurality of input operands of the configurable instructions affect a result of the configurable instructions;

computer program code for determining a measure of dissimilarity between the configurable instructions corresponding to the number of the bits of the input operands that do not affect the result of all configurable instructions for which the measure of dissimilarity is computed; and

computer program code for selecting the combination of configurable instructions on a basis of the measure of dissimilarity possible combinations with relatively less dissimilarity being preferred in the selection over possible combinations with relatively more dissimilarity.