Diagnosis of combinational logic circuit failures

• US 6,721,914 B2
• Filed: 04/06/2001
• Issued: 04/13/2004
• Est. Priority Date: 04/06/2001
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: International Business Machines Corporation
• Inventors: Huisman, Leendert M., Heaberlin, Douglas C., Bartenstein, Thomas W.
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): ABRAHAM, ESAW T
• Application Number:
  US09/827,425
• Publication Number:
  US 20020147952A1
• Time in Patent Office: 1,103 Days
• Field of Search: 714/25, 714/37, 714/799, 714/734, 714/735, 714/737, 714/41
• US Class Current: 714/734
• CPC Class Codes: G01R 31/317 Testing of digital circuits

Abstract

A method for diagnosing defects in an integrated circuit comprising: providing a set of failing test patterns; for each failing test pattern in the set of test patterns determining if a single stuck-at fault could cause the failing test pattern and determining a node on which a defect causing the single stuck-at fault could reside; selecting those failing test patterns that could be caused by a single stuck-at fault; and for those selected failing test patterns determining a first set of sets of nodes, such that each of the selected failing test patterns could be caused by a stuck-at zero or a stuck-at one on at least one node from each set of nodes from the first set of sets of nodes.

Claims

1. A method for diagnosing defects in an integrated circuit comprising:

providing a set of failing test patterns, each failing test pattern comprising a set of values, one or more of said values being incorrect compared to a corresponding value of a set values from a corresponding expected set of passing test patterns;

for each failing test pattern in said set of test patterns determining if any single stuck-at fault could potentially cause at least one of said one or more incorrect values of said failing test pattern and for each failing test pattern determined to have potentially been caused by any single stuck-at fault, determining a set of nodes of a circuit generating said failing test patterns corresponding to said at least one of said one or more incorrect values, a node being a connection between two gates or two latches or a gate and a latch of a circuit generating said set of failing test patterns;

selecting all failing test patterns for which said sets of nodes corresponding to said at least one of said one or more incorrect values were determined; and

for those selected failing test patterns determining a first set of sets of nodes, such that all incorrect values of said selected failing test patterns could be caused by a stuck-at zero or a stuck-at one on at least one node from each set of nodes from said first set of sets of nodes.

2. The method of claim 1, wherein determining a set of nodes corresponding to said at least one of said one or more incorrect values includes:

designating said selected test patterns as target faults;

simulating each said target fault against a fault machine to generate simulated fail patterns; and

determining if any of said simulated fail patterns matches said selected test pattern.

3. The method of claim 2, wherein determining said set of nodes corresponding to said at least one at least one of said one or more incorrect values further includes performing a trace back starting from a failing logic block output and terminating at a previous latch.

4. The method of claim 1, wherein determining said first set of sets of nodes further includes:

determining the size of each of said sets of nodes;

determining a set of minimal sets of nodes, said minimal sets of nodes having a minimal size; and

discarding all sets or nodes having a size higher than said minimal set size.

5. The method of claim 4, further comprising:

determining whether there is a second set of sets of nodes such that each minimal set of said set of minimal sets of nodes corresponds to a set of nodes obtained by taking one node from each set of nodes from said second set of sets of nodes and such that each set of nodes obtained by taking one node from each set of nodes from said second set of sets of nodes corresponds to one minimal set of nodes from said set of minimal sets of nodes.

6. The method of claim 1, further comprising testing said integrated circuit to obtain said set of failing test patterns.

7. A method for diagnosing defects in an integrated circuit comprising:

(a) providing a set of failing test patterns, each failing test pattern comprising a set of values, one or more of said values being incorrect compared to a corresponding value of a set values from a corresponding expected set of passing test patterns;

(b) selecting a failing test pattern from said set of failing patterns;

(c) creating one or more single stuck-at fault target faults, said target faults including single stuck-at faults that could cause at least one of said one or more incorrect values of said failing test pattern and adding said target faults to a set of target faults;

(d) selecting a target fault from said set of target faults;

(e) simulating said selected target fault against a fault machine to create a simulated fail pattern;

(f) comparing said simulated fail pattern to said selected fail pattern;

(g) if said simulated fail pattern matches said selected failing pattern, determining a set of nodes corresponding to said at least one of said one or more incorrect values, a node being a connection between two gates or two latches or a gate and a latch of said circuit and adding said set of nodes to an explaining node list for said selected failing pattern, otherwise going to step (h);

(h) repeating steps (d) through (g) until all target faults in said set of target faults have been selected;

(i) repeating stops (b) through (h) until all failing test patterns in said set of failing test patterns have been selected;

(j) selecting in turn, the nodes associated with each failing test pattern from said explaining node list and creating explaining sets of nodes for each failing test pattern; and

(k) for each failing text pattern, selecting a first set of said sets of explaining nodes such that all incorrect values of each failing test pattern could be caused by a stuck-at zero or a stuck-at one on at least one node from each set of nodes from said first set of sets of nodes.

8. The method of claim 7, wherein said target faults are generated using a set of main faults generated from a logic design corresponding to said integrated circuit, said main faults comprising at least all stuck-at faults on all nodes in the design of said integrated circuit design.

9. The method of claim 7, wherein creating one or more single stuck-at fault target faults includes performing a trace back starting from a failing logic block output and terminating at a previous logic block.

10. The method of claim 7, wherein determining said first set of said sets of nodes further includes:

determining the size of each of said sets of nodes;

determining a set of minimal sets of nodes, said minimal sets of nodes having a minimal size; and

discarding all sets of nodes having a size higher than said minimal set size.

11. The method of claim 10, further comprising:

determining whether there is a second set of sets of nodes such that each minimal set of said set of minimal sets of nodes corresponds to a set of nodes obtained by taking one node from each set of nodes from said second set of sets of nodes and such that each set of nodes obtained by taking one node from each set of nodes from said second set of sets of nodes corresponds to one minimal set or nodes from said set of minimal sets of nodes.

12. The method of claim 7, further comprising testing said integrated circuit to obtain said set of failing test patterns.