Semiconductor wafer comprising micro-machined components and a method for fabricating the semiconductor wafer

• US 6,723,579 B2
• Filed: 07/12/2002
• Issued: 04/20/2004
• Est. Priority Date: 07/12/2002
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Blackstone, Scott Carlton, Gormley, Colin Stephen, Brown, Stephen Alan
• Primary Examiner(s): Mulpuri, Savitri
• Application Number:
  US10/194,392
• Publication Number:
  US 20040009624A1
• Time in Patent Office: 648 Days
• Field of Search: 438/48-54, 438/72, 438/67, 438/106, 438/107, 438/455, 438/456, 438/457, 438/700, 438/719, 216/2, 257/414, 359/224
• US Class Current: 438/48
• CPC Class Codes: B81B 2201/042 Micromirrors, not used as optical switches
• CPC Class Codes: B81C 1/00357 involving bonding one or several substrates on a non-temporary support, e.g. another substrate
• CPC Class Codes: B81C 2201/019 Bonding or gluing multiple substrate layers
• CPC Class Codes: G02B 26/0841 the reflecting element being moved or deformed by electrostatic means

Abstract

A semiconductor wafer having a matrix array of micro-mirrors comprises a component substrate carried on a base substrate. The component substrate comprises a membrane layer in which the micro-mirrors are formed and a supporting handle layer. The base substrate comprises a base layer from which a plurality of pedestals extend upwardly therefrom into cavities in the handle layer corresponding to the micro-mirrors. Each pedestal carries electrodes for co-operating with the micro-mirrors for tilting thereof. Conductors through vias in the pedestals connect the electrodes to electrically conductive tracks on a bottom surface, and in turn through conductors through vias to addressing terminals for addressing the electrodes. By forming the pedestals in the base substrate and projecting the pedestals into the cavities in the handle layer the handle layer is recessed into the base substrate thereby facilitating the provision of a handle layer of depth sufficient for adequately supporting the membrane layer during fabrication of the wafer.

Claims

1. A method for fabricating a semiconductor wafer comprising a plurality of micro-machined components formed therein, the method comprising the steps of:

fabricating a component substrate having a membrane layer supported on a handle layer,

forming the micro-machined components spaced apart from each other in the membrane layer,

forming a plurality of cavities in the handle layer corresponding to the micro-machined components, each cavity extending through the handle layer to the corresponding micro-machined component,

forming a support substrate having a first surface facing in a first direction and defining a second surface facing in a second direction away from and opposite to the first direction and defining an intermediate surface at a level intermediate the first and second surfaces facing in the second direction,

forming a plurality of spaced apart pedestals in the support substrate corresponding to the cavities, the pedestals extending from the intermediate surface in the second direction and terminating in the second surface,

forming at least one electrode on the second surface of each pedestal,

forming a plurality of electrically conductive addressing tracks on one of the first and the intermediate surfaces of the support substrate for carrying signals to be conducted to the respective electrodes,

forming a via through each pedestal corresponding to each electrode, each via extending from the second surface of the corresponding pedestal for accommodating a corresponding electrical conductor from the electrode to the corresponding one of the addressing tracks,

forming the electrical conductors in the respective vias for connecting the corresponding electrodes to the corresponding addressing tracks, and

joining the component substrate to the support substrate so that the pedestals extend into respective corresponding ones of the cavities in the handle layer of the support substrate with the second surfaces defined by the pedestals spaced apart from the corresponding micro-machined components for accommodating movement of the micro-machined components, and the electrodes of the pedestals co-operating with the corresponding micro-machined components.

2. A method as claimed in claim 1 in which a plurality of mutually insulated electrodes are formed on each pedestal, and a corresponding number of vias and electrical conductors are formed through each pedestal for connecting the respective electrodes to corresponding ones of the respective addressing tracks.

3. A method as claimed in claim 1 in which the vias through the pedestals are formed prior to forming the electrodes thereon.

4. A method as claimed in claim 1 in which a plurality of mutually insulated addressing terminals are formed on the support substrate and are electrically connected to respective corresponding ones of the addressing tracks for addressing corresponding ones of the electrodes.

5. A method as claimed in claim 4 in which a terminal carrier is formed on the support substrate extending from the intermediate surface in the second direction, the addressing terminals being formed on the terminal carrier, a plurality of vias corresponding to the respective addressing terminals are formed extending from the corresponding ones of the addressing terminals through the terminal carrier for accommodating corresponding electrically conductors from the addressing terminals to the corresponding addressing tracks, and the electrical conductors are formed in the respective vias through the terminal carrier for communicating the addressing terminals with the corresponding ones of the addressing tracks for facilitating addressing of the respective electrodes through the corresponding addressing tracks from the corresponding addressing terminals.

6. A method as claimed in claim 5 in which the terminal carrier terminates in the second surface of the support substrate, and the addressing terminals are formed on the second surface of the terminal carrier.

7. A method as claimed in claim 2 in which the addressing tracks are formed on the first surface of the support substrate.

8. A method as claimed in claim 1 in which each via in each pedestal extends through the support substrate to the corresponding addressing track.

9. A method as claimed in claim 1 in which the addressing tracks are formed on the intermediate surface of the support substrate, and each via in each pedestal extends to the corresponding addressing track.

10. A method as claimed in claim 1 in which the handle layer defines a first surface of the component substrate, the first surface facing in the first direction, and the component substrate and the support substrate are joined with the first surface of the component substrate abutting the intermediate surface of the support substrate.

11. A method as claimed in claim 1 in which the support substrate is formed by joining a pedestal layer to a base layer, the base layer defining the first surface of the support substrate, and forming the pedestals in the pedestal layer.

12. A method as claimed in claim 11 in which the pedestal layer is patterned by a photo-lithographic process and is then etched for forming the pedestals.

13. A method as claimed in claim 5 in which the terminal carrier is formed in the pedestal layer during etching of the pedestal layer for forming the pedestals.

14. A method as claimed in claim 11 in which an insulating layer is formed between the pedestal layer and the base layer.

15. A method as claimed in claim 14 in which the pedestal layer is etched down to the insulating layer, which acts as an etch stop layer during forming the pedestals.

16. A method as claimed in claim 1 in which an insulating layer is formed between the handle layer and the membrane layer of the component substrate.

17. A method as claimed in claim 16 in which the insulating layer formed between the handle layer and the membrane layer in the component substrate is etched through the corresponding cavities in the handle layer for exposing the micro-matched components in the corresponding cavities.

18. A method as claimed in claim 16 in which the first surface of the handle layer of the component substrate is patterned by a photo-lithographic process for defining the cavities, and the cavities are then etched through the handle layer.

19. A method as claimed in claim 18 in which the insulating layer between the handle layer and the membrane layer of the component substrate acts as an etch stop layer during etching of the cavities in the handle layer.