Pixel cell with high storage capacitance for a CMOS imager

• US 6,723,594 B2
• Filed: 03/04/2002
• Issued: 04/20/2004
• Est. Priority Date: 02/25/2000
• Status: Expired due to Term

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Rhodes, Howard E.
• Primary Examiner(s): Pert, Evan
• Assistant Examiner(s): KILDAY, LISA A
• Application Number:
  US10/086,535
• Publication Number:
  US 20020096733A1
• Time in Patent Office: 778 Days
• Field of Search: 257/218, 257/222, 257/232, 257/443, 257/462, 438/199, 438/200, 438/202, 438/217, 438/592, 438/655, 438/656
• US Class Current: 438/200
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers

Abstract

A pixel sensor cell for use in a CMOS imager exhibiting improved storage capacitance. The source follower transistor is formed with a large gate that has an area from about 0.3 μm² to about 10 μm². The large size of the source follower gate enables the photocharge collector area to be kept small, thereby permitting use of the pixel cell in dense arrays, and maintaining low leakage levels. Methods for forming the source follower transistor and pixel cell are also disclosed.

Claims

1. A method of forming a source follower transistor for use in a CMOS imaging device, said method comprising the steps of:

forming a doped layer in a substrate;

forming a first doped region and a second doped region in the doped layer;

forming an insulating layer on the doped layer between the first and the second doped regions;

forming a gate layer on the insulating layer, wherein the gate layer having an active area of from about 0.3 μ

m² to about 25 μ

m², and wherein the gate layer is adapted to be electrically connected to receive charge from a photocharge collector.

2. The method of claim 1, wherein the photocharge collector is a photodiode.

3. The method of claim 1, wherein the doped layer forming step includes ion implantation of at least one dopant into the substrate.

4. The method of claim 1, wherein the doped region forming step includes ion implantation of at least one dopant into the substrate.

5. The method of claim 1, wherein the doped layer is doped to a first conductivity type, and the doped regions are doped to a second conductivity type.

6. The method of claim 5, wherein the first conductivity type is p-type, and the second conductivity type is n-type.

7. The method of claim 1, wherein the insulating layer is formed by thermal oxidation.

8. The method of claim 7, wherein the insulating layer is a layer of silicon dioxide.

9. The method of claim 1, wherein the insulating layer is formed by chemical vapor deposition.

10. The method of claim 9, wherein the insulating layer is a layer of silicon nitride.

11. The method of claim 1, wherein the gate layer is a layer of doped polysilicon.

12. The method of claim 1, wherein the gate layer is a layer of tungsten.

13. The method of claim 1, wherein said step of forming a gate layer includes formation of a polysilicon layer on the insulating layer, followed by formation of a metal layer on the polysilicon layer, followed by annealing to form a metal silicide layer from the polysilicon layer and the metal layer.

14. The method of claim 13, wherein the gate layer is a layer of tungsten silicide.

15. A method of forming a pixel cell for use in a CMOS imaging device, said method comprising the steps of:

forming a doped layer in a substrate;

forming a photocharge collector on said doped layer; and

forming a source follower transistor having a gate on said doped layer, wherein the gate having an active area of from about 0.3 μ

m² to about 25 μ

m².

16. The method of claim 15, wherein the photocharge collector is a photodiode.

17. The method of claim 15, further comprising forming a contact between the photodiode and the gate.

18. The method of claim 15, further comprising forming a doped region in the doped layer adjacent to the photodiode.

19. The method of claim 18, wherein the doped layer is doped to a first conductivity type, and the doped region is doped to a second conductivity type.

20. The method of claim 18, further comprising forming a contact between the doped region and the gate.

21. The method of claim 18, further comprising forming a transfer gate on the doped layer between the doped region and the photodiode.

22. A CMOS imager device comprising:

means for establishing a reference voltage;

means for storing a photocharge in a surface well of said CMOS imager, said photocharge functionally related to an intensity of incident photons impinging on a photogate of said imager;

means for transferring said photocharge to a gate of a control transistor, said gate having an active area of from about 0.3 μ

m² to about 25 μ

m², said control transistor adapted to control a photovoltage functionally related to said photocharge;

means for comparing said photovoltage to said reference voltage to produce a difference signal substantially equal to an arithmetic difference between said photovoltage and said reference voltage.

23. A CMOS imager device as defined in claim 22, wherein said means for transferring said photocharge to said gate of said control transistor further comprises:

a transfer transistor adapted to receive a transfer signal at a gate thereof.

24. A CMOS imager as defined in claim 22, wherein said means for establishing a reference voltage comprises:

a reference sample and hold circuit having a first sample and hold capacitor operatively coupled between a respective gate and drain of said reference sample and hold transistor.

25. A CMOS imager as defined in claim 24, wherein said means for comparing said photovoltage to said reference voltage comprises:

a pixel sample and hold circuit having a pixel sample and hold capacitor operatively coupled between a respective gate and drain of a pixel sample and hold transistor; and

a subtractor circuit coupled to said reference and pixel sample and hold transistors, said subtractor circuit adapted to receive respective signals from said reference and pixel sample and hold transistors and produce said difference signal.

26. A processor system for capturing an optical image comprising:

a central processing unit;

an imager unit coupled to said central processing unit, said imager unit having a source follower transistor including a source region formed in a substrate, a drain region formed in the substrate, a gate layer formed on the substrate between said source region and said drain region, wherein said gate layer has an active area of from about 0.3 μ

m² to about 25 μ

m², and wherein said gate layer is adapted to be electrically connected to receive a charge from a photocharge collector;

a sample and hold circuit coupled to said source follower transistor, said sample and hold circuit adapted to receive a first analog signal controlled by said source follower transistor as input and to output a second analog signal related to said first analog signal; and

an analog to digital converter coupled to said sample and hold circuit and adapted to receive said second analog signal therefrom, said analog to digital converter adapted to output a first digital signal related to said second analog signal.

27. A processor system as defined in claim 26, wherein said photocharge collector is a photodiode.

28. A processor system as defined in claim 26, further comprising:

a random access memory coupled to said central processing unit, said random access memory adapted to receive a second digital signal generated by said central processor in response to said first digital signal.

29. A processor system as defined in claim 26, further comprising:

a long-term storage device, such as a floppy disk, coupled to said central processing unit, said long-term storage device adapted to receive and store a second digital signal generated by said central processor in response to said first digital signal.