Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming

• US 6,723,604 B2
• Filed: 10/03/2002
• Issued: 04/20/2004
• Est. Priority Date: 09/22/2000
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Yuan, Jack H., Haskell, Jacob
• Primary Examiner(s): Mai, Son
• Assistant Examiner(s): Le, Thao P.
• Application Number:
  US10/265,066
• Publication Number:
  US 20030031068A1
• Time in Patent Office: 565 Days
• Field of Search: 365/185.14, 438/257
• US Class Current: 438/257
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0458 comprising two or more independent floating gates which store independent data
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called “shallow trench isolation” or “STI.” Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made of doped polysilicon, that extend in the column direction on top of the substrate. This structure is implemented in a flash memory array of cells having either one floating gate per cell or at least two floating gates per cell. A process of making a dual-floating gate memory cell array includes etching the word lines twice along their lengths, once to form openings through which source and drain implants are made and in which the conductive bit lines are formed, and second to form individual floating gates with a select transistor gate positioned between them that also serves to erase charge from the adjacent floating gates.

Claims

1. A method of forming an array of floating gate memory cells on a substrate from a plurality of parallel elongated strips of gate material positioned along rows of cells, comprising:

separating the strips into segments of a given length with a first set of spaces therebetween,

implanting ions into regions of the substrate through said first set of spaces in a manner that said regions are isolated from each other along and between the rows,

forming conductive lines in the first set of spaces that individually electrically contact a plurality of said substrate regions in a plurality of rows,

separating the strip segments into sub-segments having a second set of spaces therebetween, and

forming control gates along the rows over said sub-segments and conductive lines, and which extend into the second set of spaces adjacent to edges of said sub-segments with tunnel dielectric therebetween.

2. The method of claim 1 which additionally comprises forming trenches in the substrate between the strips of gate material and filling the trench with a dielectric material.

3. The method of either of claims 1 or 2, wherein the conductive lines are formed of doped polycrystalline silicon material.

4. A method of constructing an array of non-volatile memory cells on a substrate, comprising:

forming a plurality of trenches in the substrate that are elongated in a first direction across the substrate and spaced apart in a second direction across the substrate, the first and second directions being orthogonal to each other,

filling said plurality of trenches with a dielectric material,

forming a first layer of gate material in strips having lengths extending in the first direction and spaced apart in the second direction to lie between the dielectric filled trenches,

forming over the first layer of gate material a second layer of gate material in strips having lengths extending in the second direction and being spaced apart in the first direction,

covering with a first mask a first set of spaces between the second gate material layer strips including every other space across the substrate in the first direction and leaving exposed a second set of spaces between the second gate material layer strips including remaining every other space across the substrate in the first direction and in between the first set of spaces,

etching the first gate material layer strips through the exposed second set of spaces,

implanting ions into the substrate through the exposed second set of spaces, thereby to form source and drain regions in the substrate,

thereafter forming conductive strips within the exposed second set of spaces that are elongated in the second direction and individually electrically contact a plurality of the source and drain regions along their lengths,

removing the first mask to expose the first set of spaces,

etching the first gate material layer strips through the exposed first set of spaces, thereby exposing edges of the first layer strips,

forming layers of tunnel dielectric on the exposed first layer strip edges, and

thereafter forming from a third layer of gate material control gates having lengths extending in the first direction over the first and second gate material layers with the conductive strips extending into the first set of spaces in contact with the tunnel dielectric, thereby to serve as erase gates.