Method of preventing leakage current of a metal-oxide semiconductor transistor
First Claim
1. A method of fabricating a metal-oxide semiconductor transistor (MOS transistor) on a substrate comprising:
- sequentially forming a gate oxide layer and a gate on the substrate;
performing a first ion implantation process to form a first doped region in the substrate;
sequentially forming a liner layer, a dielectric layer and a sacrificial layer on the substrate;
performing a first etching process to simultaneously form an arc-shaped spacer on either side of the gate and remove portions of the dielectric layer and the sacrificial layer atop the gate by utilizing the liner layer as a first stop layer;
performing a second etching process to remove portions of the sacrificial layer within the arc-shaped spacer by utilizes the dielectric layer as a second stop layer, and constructing a L-shaped spacer on either side of the gate;
performing a third etching process to remove portions of the liner layer not covered by the L-shaped spacer;
performing a second ion implantation process to form a second doped region with a gradient profile in portions of the substrate adjacent to either side of the L-shaped spacer; and
performing a self-aligned silicide (salicide) process to form a silicide layer on the gate and on exposed portions of the substrate surface above the second doped region.
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Abstract
A gate oxide layer and a gate are sequentially formed on a substrate, and a source/drain extension is formed in the substrate thereafter. A liner layer is then formed to cover the substrate, and a first dielectric layer and a second dielectric layer are sequentially formed on the liner layer. By performing an etching process, a L-shaped spacer is formed on either side of the gate. Portions of the liner layer uncovered by the L-shaped spacer are then removed, and a step source/drain extension and a source/drain are simultaneously formed in the substrate thereafter. Finally, a salicide process is performed to form a silicide layer on the gate and on portions of the silicon substrate surface above the source/drain.
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Citations
19 Claims
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1. A method of fabricating a metal-oxide semiconductor transistor (MOS transistor) on a substrate comprising:
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sequentially forming a gate oxide layer and a gate on the substrate;
performing a first ion implantation process to form a first doped region in the substrate;
sequentially forming a liner layer, a dielectric layer and a sacrificial layer on the substrate;
performing a first etching process to simultaneously form an arc-shaped spacer on either side of the gate and remove portions of the dielectric layer and the sacrificial layer atop the gate by utilizing the liner layer as a first stop layer;
performing a second etching process to remove portions of the sacrificial layer within the arc-shaped spacer by utilizes the dielectric layer as a second stop layer, and constructing a L-shaped spacer on either side of the gate;
performing a third etching process to remove portions of the liner layer not covered by the L-shaped spacer;
performing a second ion implantation process to form a second doped region with a gradient profile in portions of the substrate adjacent to either side of the L-shaped spacer; and
performing a self-aligned silicide (salicide) process to form a silicide layer on the gate and on exposed portions of the substrate surface above the second doped region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
forming a metal layer on the gate and on portions of the substrate surface above the source/drain;
performing a first rapid thermal process (RTP);
performing a wet etching process to remove unreacted portions of th metal layer on th surface of the substrate; and
performing a second RTP.
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8. The method of claim 7 wherein the metal layer comprises cobalt (Co).
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9. The method of claim 1 wherein the first and second doped regions are doped with either arsenic (As) atoms or phosphorus (P) atoms.
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10. The method of claim 1 wherein the first and second doped region are doped with either one of boron difluoride (BF2+) ions, boron (B) atoms or indium (In) atoms.
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11. A method of fabricating a MOS transistor on a substrate comprising:
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sequentially forming a gate oxide layer and a gat on the substrate;
performing a first ion implantation process to form a first doped region in the substrate;
forming a liner layer to cover the substrate;
sequentially forming a dielectric layer and a sacrificial layer on the lin r layer;
performing a first etching process to simultaneously form an arc-shaped spacer on either side of the gate and remove portions of the dielectric layer and the sacrificial layer atop the gate by utilizing the liner layer as a first stop layer;
performing a second etching process to remove portions of the sacrificial layer within the arc-shaped spacer by utilizes the dielectric layer as a second stop layer, and constructing a L-shaped spacer on either side of the gate;
performing a third etching process to remov portions of the liner layer not covered by the L-shaped spacer;
performing a second ion implantation process to simultaneously form a second doped region and a third doped region in the substrate; and
performing a salicide process to form a silicide layer on the gate and on portions of the substrat surface above the third doped region. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
forming a metal layer on the gate and on portions of the substrate surface above the third doped region;
performing a first RTP;
performing a wet etching process to remove unreacted portions of the metal layer on the surface of the substrate; and
performing a second RTP.
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19. The method of claim 18 wherein the metal layer comprises cobalt.
Specification