Emissive display device and electroluminescence display device with uniform luminance

• US 6,724,149 B2
• Filed: 02/23/2000
• Issued: 04/20/2004
• Est. Priority Date: 02/24/1999
• Status: Expired due to Term

• Current Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Nishikawa, Ryuji, Yamada, Tsutomu, Komiya, Naoaki, Yokoyama, Ryoichi
• Primary Examiner(s): Wong, Don
• Assistant Examiner(s): Dinh, Trinh Vo
• Application Number:
  US09/510,853
• Publication Number:
  US 20030076046A1
• Time in Patent Office: 1,518 Days
• Field of Search: G09/G.310, 315/169.3, 315/169.2, 315/169.1, 313/500, 313/503, 313/504, 313/505, 313/506, 313/463, 313/497, 345/76, 345/92, 345/77
• US Class Current: 315/169.3
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals

Abstract

Power source lines (183) for supplying drive current from power source input terminals (180) to organic EL elements (160) formed in a display pixel region having display pixels are connected by a bypass line (181) along the row direction within the display pixel region. This arrangement minimizes decrease in power source current caused by resistance of the power source lines (183) according to the line length. Accordingly, the organic EL elements (160) can adequately receive the actual desired current, thereby achieving an organic EL device capable of bright displays and having uniform display luminance within the display region.

Claims

1. An electroluminescence display device, comprising:

a plurality of display pixels arranged in a matrix within a display pixel region on a substrate, said display pixels having electroluminescence elements including an emissive layer between first and second electrodes;

wherein within said display pixel region, power source lines for supplying power from a power source to said electroluminescence elements are disposed in a grid pattern extending in row and column directions of the matrix,

wherein said power source lines include main power source lines arranged in plural numbers along the column direction of said matrix within said display pixel region, and at least one bypass power source line extended in the row direction of said matrix within said display pixel region to intersect and connect said main power lines,

wherein said main power source lines and said bypass power source line are conductive lines separately formed in different processes,

wherein said bypass power source line is formed in a layer located underneath said main power source lines and separated from said main power source lines by an insulating layer, and is connected to said main power source lines via contact holes.

2. The device defined in claim 1, wherein said bypass power source line is formed in a same layer as a gate line.

3. The device defined in claim 1, wherein said bypass power source line is formed on a gate insulating film, and an interlayer insulating film that separates an active layer of said second thin film transistor and said main power source lines is provided between said bypass power source line and said main power source lines as said insulating layer.

4. An electroluminescence display device, comprising:

a display pixel region having a plurality of display pixels arranged in a matrix, wherein each of said display pixels includes;

an electroluminescence element having an emissive layer between an anode and a cathode;

a first thin film transistor having a gate electrode connected to a gate line, and a first electrode region connected to a data line; and

a second thin film transistor having a gate electrode connected to a second electrode region of said first thin film transistor, a first electrode region connected to power source lines for supplying power from a power source to said electroluminescence element, and a second electrode region connected to said electroluminescence element;

wherein said power source lines are provided along a column direction of said matrix within said display pixel region, and those power source lines that are associated with the display pixels adjacently arranged along a row direction are connected to one another by a bypass power source line extending in the row direction of said matrix,

wherein said power source lines and said bypass power source line are conductive lines separately formed in different processes,

wherein said bypass power source line is formed in a layer located underneath main power source lines and separated from said main power source lines by an insulating layer, and is connected to said main power source lines via contact holes.

5. The device defined in claim 4, wherein said bypass power source line is formed in a same layer as a gate line.

6. The device defined in claim 4, wherein said bypass power source line is formed on a gate insulating film, and an interlayer insulating film that separates an active layer of said second thin film transistor and said main power source lines is provided between said bypass power source line and said main power source line as said insulating layer.

7. An emissive display device comprising:

a plurality of display pixels arranged in a matrix within a display pixel region, each of said display pixels having emissive elements including an emissive layer between first and second electrodes;

wherein within said display pixel region, power source lines for supplying power from a power source to said emissive elements are disposed in a grid pattern extending in row and column directions of the matrix,

wherein said power source lines include main power source lines arranged in plural numbers along the column direction of said matrix within said display pixel region, and at least one bypass power source line extended in the row direction of said matrix within said display pixel region to intersect and connect said main power lines,

wherein said main power source lines and said bypass power source line are conductive lines separately formed in different processes,

wherein said bypass power source line is formed in a layer located underneath said main power source lines and separated from said main power source lines by an insulating layer, and is connected to said main power source lines via contact holes.

8. The device defined in claim 7, wherein said bypass power source line is formed in a same layer as a gate line.

9. The device defined in claim 7, wherein said bypass power source line is formed on a gate insulating film, and an interlayer insulating film that separates an active layer of said second thin film transistor and said main power source lines is provided between said bypass power source line and said main power source lines as said insulating layer.