Controller for power device and drive controller for motor
First Claim
1. A controller for controlling a power device in response to an input signal wherein said power device includes a series connection of a first and second semiconductor device which are connected between first and second main power supply potentials with the conduction of at least said first semiconductor device being controlled by a control signal and with a common node of said first and second semiconductor device providing an output and with said input signal being generated as a function of said second main power supply potential, said controller comprising:
- first signal generating means for generating a first signal in response to said input signal;
level shift means for changing an output level of said first signal to a value which is a function of said first main power supply potential in order to produce a second signal; and
a first control signal generator means for generating said control signal for said first semiconductor device in response to said second signal, wherein said level shift means includes at least one level shifting semiconductor element wherein said semiconductor element is controlled by said first signal and said at least one level shifting semiconductor element exhibiting breakdown voltage characteristics whereby a breakdown voltage has a value not less than a voltage in the range between a value of said first and a value of said second main power supply potential.
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Abstract
A controller for controlling a power device in response to an input signal includes a first signal generator for generating a first signal in response to the input signal; a level shifter for changing an output level of the first signal to a value which is a function of a first main power supply potential in order to produce a second signal; and a first control signal generator for generating the control signal for a first semiconductor device in response to the second signal. The level shifter includes at least one level shifting semiconductor element wherein the semiconductor element is controlled by the first signal and the at least one level shifting semiconductor element exhibiting breakdown voltage characteristics whereby a breakdown voltage has a value not less than a voltage in the range between a value of the first and a value of a second main power supply potential.
38 Citations
17 Claims
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1. A controller for controlling a power device in response to an input signal wherein said power device includes a series connection of a first and second semiconductor device which are connected between first and second main power supply potentials with the conduction of at least said first semiconductor device being controlled by a control signal and with a common node of said first and second semiconductor device providing an output and with said input signal being generated as a function of said second main power supply potential, said controller comprising:
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first signal generating means for generating a first signal in response to said input signal;
level shift means for changing an output level of said first signal to a value which is a function of said first main power supply potential in order to produce a second signal; and
a first control signal generator means for generating said control signal for said first semiconductor device in response to said second signal, wherein said level shift means includes at least one level shifting semiconductor element wherein said semiconductor element is controlled by said first signal and said at least one level shifting semiconductor element exhibiting breakdown voltage characteristics whereby a breakdown voltage has a value not less than a voltage in the range between a value of said first and a value of said second main power supply potential. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
said second signal is a shifted pulse obtained by level-shifting said pulse by said level shift means, and said control signal generator means includes latch means for latching said shifted pulse to generate said control signal for said first semiconductor device. -
3. The controller of claim 2, wherein:
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said pulse generator means generates first and second pulses in response to positive and negative level transitions of said input signal, respectively, with said first and second pulses constituting said first signal, said level shift means includes first and second level shifting semiconductor elements provided between said first and second main power supply potentials and having a breakdown voltage characteristic which is not less than a voltage between said first and second main power supply potentials, said first and second level shifting semiconductor elements level-shifting said first and second pulses toward said first main power supply potential to generate first and second shifted pulses, thereby to provide said second signal, and said latch means latches said second signal including said first and second shifted pulses to use said second signal as said control signal for said first semiconductor device.
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4. The controller of claim 3, further comprising:
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first operation abnormality detector means for detecting an abnormal operation in said first semiconductor device to generate a first abnormality indication signal having a level based on said first main power supply potential, said level shift means further includes a third level shifting semiconductor element provided between said first and second main power supply potentials and having a breakdown voltage characteristic which is not less than a voltage between said first and second main power supply potentials, said third level shifting semiconductor element level-shifting said first abnormality indication signal toward said second main power supply potential to produce a second abnormality indication signal, and said second abnormality indication signal is a feedback signal to a circuit for generation of said input signal.
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5. The controller of claim 4, wherein:
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said first operation abnormality detector means includes abnormality indication signal pulse generator means for generating a pulse in response to level transition of said first abnormality indication signal to use said pulse as a pulse signal for said first abnormality indication signal, said second abnormality indication signal is a shifted pulse obtained by level-shifting said pulse signal for said first abnormality indication signal by said third level shifting semiconductor element, and said level shift means includes feedback signal latch means for latching said shifted pulse as said second abnormality indication signal to generate said feedback signal to said circuit for generation of said input signal.
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6. The controller of claim 5, wherein:
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a first controllable semiconductor element included in said first semiconductor circuit and said first and second level shifting semiconductor elements are of a first conductivity type, and said third level shifting semiconductor element is of a second conductivity type.
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7. The controller of claim 6, wherein:
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said control signal for said first controllable semiconductor element is a first control signal, said second semiconductor device includes a second controllable semiconductor element, controllable in response to a second control signal, said controller further comprising;
second control signal generator means for generating said second control signal in response to said input signal.
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8. The controller of claim 7, further comprising:
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a current detecting resistor between an electrode of said second controllable semiconductor element which outputs a main current and said second main power supply potential for detecting and converting said main current flowing through said second controllable semiconductor element into a voltage signal corresponding to said main current; and
analog signal output means receiving said voltage signal corresponding to said main current for feeding back a value of said main current indicated by said voltage signal to said second control signal generator means in the form of an analog signal.
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9. The controller of claim 8, wherein said analog signal output means includes:
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delay signal generator means for causing said second control signal to delay to generate a delay signal;
a gate element having an input and an output and receiving said voltage signal at said input for opening and closing a transmission path of said voltage signal from said input to said output in response to said delay signal; and
a capacitor between said output of said gate element and said second main power supply potential, and wherein said analog signal is provided at said output.
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10. The controller of claim 4, further comprising:
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second operation abnormality detector means for detecting an abnormal operation in said second semiconductor circuit to generate a third abnormality indication signal having a level based on said second main power supply potential; and
abnormality indication signal identifying means for identifying said second and third abnormality indication signals to feed back a result of the identification to said circuit for generation of said input signal.
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11. The controller of claim 7, further comprising:
input interlock means for detecting timings of generation of said first and second control signals to prevent said first and second control signals from being outputted simultaneously.
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12. The controller of claim 7, further comprising:
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PWM signal generator means for generating first and second PWM signals in response to said input signal, said first and second control signals being generated in response to said first and second PWM signals, respectively.
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13. The controller of claim 1, wherein said controller is integrated on a single or a plurality of semiconductor substrates and is driven by a single operation power supply for feeding a voltage between said first and second main power supply potentials.
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14. A drive controller for a motor, comprising:
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a controller for controlling a power device in response to an input signal wherein said power device includes a series connection of a first and second semiconductor device which are connected between first and second main power supply potentials with the conduction of at least said first semiconductor device being controlled by a control signal and with a common node of said first and second semiconductor device providing an output and with said input signal being generated as a function of said second main power supply potential, said controller comprising;
first signal generating means for generating a first signal in response to said input signal;
level shift means for changing an output level of said first signal to a value which is a function of said first main power supply potential in order to produce a second signal; and
a first control signal generator means for generating said control signal for said first semiconductor device in response to said second signal, wherein said level shift means includes at least one level shifting semiconductor element wherein said semiconductor element is controlled by said first signal and said at least one level shifting semiconductor element exhibiting breakdown voltage characteristics whereby a breakdown voltage has a value not less than a voltage in the range between a value of said first and a value of said second main power supply potential;
wherein said controller is integrated on a single or a plurality of semiconductor substrates and is driven by a single operation power supply for feeding a voltage between said first and second main power supply potentials;
a brake circuit in parallel with said first and second semiconductor devices for applying an electrical brake to said motor in response to a predetermined stop signal; and
a converter circuit for rectifying an AC power supply to provide said first and second main power supply potentials, said first and second semiconductor devices, said controller, said brake circuit and said converter circuit being provided in the form of a module. - View Dependent Claims (15, 16, 17)
a charge pump circuit between said power supply circuit and a connection point of said first and second semiconductor devices, said charge pump circuit including a first diode and a capacitor connected in series in order from a positive output of said power supply circuit; and
a second diode between said first diode and a control electrode of said first controllable semiconductor element of said first semiconductor device, said second diode having a negative electrode connected to a negative electrode of said first diode.
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Specification