FM demodulator having DC offset compensation

• US 6,724,247 B2
• Filed: 09/05/2002
• Issued: 04/20/2004
• Est. Priority Date: 09/13/2001
• Status: Expired due to Term

• Current Assignee: Unwired Planet LLC (JP Morgan Chase & Co)
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Mattisson, Sven, Haartsen, Jacobus C.
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US10/234,180
• Publication Number:
  US 20030090317A1
• Time in Patent Office: 593 Days
• Field of Search: 329/300-303, 329/315, 329/318-321, 375/317, 375/319, 375/324, 375/334-337, 455/205, 455/214, 455/337
• US Class Current: 329/318
• CPC Class Codes: H03D 3/005 wherein the demodulated signal is used for controlling a bandpass filter automatic bandwidth control H03G; automatic frequency control H03J7/02
• CPC Class Codes: H03K 9/06 of frequency- or rate-modulated pulses

Abstract

An FM demodulator compensates for DC offset by detecting the positive peak value of the frequency demodulated signal (D1, C2, R1) and the negative peak value of the frequency demodulated signal (D2, C3, R2). The mean of the positive and negative peak values is determined (C1, R3, R4) to produce an estimation of a DC offset value. This estimated DC offset value is then used to compensate for DC offset in the frequency demodulated signal. This circuit has the advantage of enabling the DC offset to be calculated without requiring complex digital signalling processing, and without requiring the input signal to have a zero mean. A signal strength signal RSSI may be used to disconnect the DC offset compensation circuitry during periods when the input signal strength is weak.

Claims

1. A frequency modulated signal demodulator including a DC offset compensation circuit, wherein the DC offset compensation circuit comprises:

means for deriving the positive and negative peak values of a frequency demodulated signal;

means for determining the mean of the positive and negative peak values as an estimate of a DC offset value; and

,

means for utilising this estimated DC offset value to compensate for DC offset in the frequency demodulated signal;

an input for receiving the frequency demodulated signal;

an output for an estimated DC offset signal;

a pair of diodes connected in parallel with opposite polarity, between the input and output;

a resistor connected in parallel with the pair of diodes; and

an output capacitor connected between the output and a ground terminal.

2. A demodulator as claimed in claim 1, wherein at least one diode is replaced by an active circuit which simulates the function of a diode.

3. A demodulator as claimed in claim 2, wherein the voltage drop of the active circuit is turnable.

4. A frequency modulated signal demodulator including a DC offset compensation circuit, wherein the DC offset compensation circuit comprising;

means for deriving the positive and negative peak values of a frequency demodulated signal;

means for determining the mean of the positive and negative peak values as an estimate of a DC offset value; and

,

means for utilising this estimated DC offset value to compensate for DC offset in the frequency demodulated signal;

an input for receiving a frequency demodulated signal;

an output for an estimated DC offset signal;

a first diode having its cathode connected to the input and its anode connected to a ground terminal via a first capacitor, wherein the anode is also connected to a negative supply terminal via a first resistor and to the output via a second resistor;

a second diode having its anode connected to the input and its cathode connected to a ground terminal via a second capacitor, wherein the cathode is also connected to a positive supply terminal via a third resistor and to the output via a fourth resistor; and

an output capacitor connected between the output and a ground terminal.

5. A demodulator as claimed in claim 4, wherein the DC offset compensation circuit further comprises:

a pair of diodes connected in parallel with opposite polarity, between the anode and cathode of the first and second diodes respectively.

6. A frequency modulated signal demodulator including a DC offset compensation circuit, wherein the DC offset compensation circuit comprises:

means for deriving the positive and negative peak values of a frequency demodulated signal;

means for determining the mean of the positive and negative peak values as an estimate of a DC offset value; and

,

means for utilising this estimated DC offset value to compensate for DC offset in the frequency demodulated;

signal strength switching means for disconnecting the frequency demodulated signal from the input of the DC offset compensation circuit during weak-signal conditions.

7. A frequency modulated signal demodulator including a DC offset compensation circuit, wherein the DC offset compensation circuit comprises;

means for deriving the positive and negative peak values of a frequency demodulated signal;

means for determining the mean of the positive and negative peak values as an estimate of a DC offset value; and

,

means for utilising this estimated DC offset value to compensate for DC offset in the frequency demodulated;

signal strength switching means for disconnecting an output capacitor from the DC offset compensation circuit during weak-signal conditions.

8. A frequency modulated signal demodulator including a DC offset compensation circuit, wherein the DC offset compensation circuit comprises:

means for deriving the positive and negative peak values of a frequency demodulated signal;

means for determining the mean of the positive and negative peak values as an estimate of a DC offset value; and

,

means for utilising this estimated DC offset value to compensate for DC offset in the frequency demodulated signal;

comprising signal strength switching means for disconnecting the frequency demodulated signal from the input to the DC offset compensation circuit and for disconnecting an output capacitor from the DC offset compensation circuit during weak-signal conditions.