Switched gain amplifier circuit

• US 6,724,252 B2
• Filed: 02/21/2002
• Issued: 04/20/2004
• Est. Priority Date: 02/21/2002
• Status: Expired due to Term

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Thomas, Mike B., Ngo, David Q., Foye, Christopher B.
• Primary Examiner(s): Nguyen, Patricia
• Application Number:
  US10/080,187
• Publication Number:
  US 20030155972A1
• Time in Patent Office: 789 Days
• Field of Search: 330/51, 330/129, 330/133, 330/134
• US Class Current: 330/133
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 2203/7227 the gated amplifier being switched on or off by a switch in the supply circuit of the amplifier
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03G 3/004 Control by varying the supply voltage
• CPC Class Codes: H03G 3/3042 in modulators, frequency-changers, transmitters or power amplifiers transmission power control in bidirectional transmission systems H04W52/04
• CPC Class Codes: H03G 3/3047 for intermittent signals, e.g. burst signals

Abstract

An amplifier chain that switches between a saturated mode of operation and a linear mode of operation comprises at least two amplifier stages. A switch is associated with the first amplifier stage and dampens the gain of the amplifier chain when the switch is closed. In a first embodiment, this is done by bypassing the first amplifier stage. In second and third embodiments, this is done by providing a feedback loop to the first amplifier stage. Dynamic device scaling and changing the bias may also be used to affect the performance of the amplifier chain.

Claims

1. An amplifier chain, comprising:

a first amplifier stage;

a final amplifier stage in series with said first amplifier stage;

a switch associated with said first amplifier stage;

said first and final amplifier stages operating in a saturated mode when said switch is open; and

said first amplifier stage being bypassed when said switch is closed and said final amplifier stage operating in a linear mode when said switch is closed.

2. The amplifier chain of claim 1 further comprising a second amplifier stage positioned serially between said first stage and said final stage.

3. The amplifier chain of claim 2 wherein said second amplifier stage operates in a saturated mode when said switch is open and a linear mode when said switch is closed.

4. The amplifier chain of claim 1 further comprising a bias circuit providing a bias current for biasing said final amplifier stage.

5. The amplifier chain of claim 4 wherein said bias current increases when said switch is closed.

6. The amplifier chain of claim 1 wherein said final amplifier stage comprises a transistor array.

7. The amplifier chain of claim 2 wherein said second amplifier stage comprises a plurality of parallel transistor cells.

8. The amplifier chain of claim 7 wherein said final amplifier stage comprises a second plurality of parallel transistor cells.

9. The amplifier chain of claim 1 wherein said switch comprises a pin diode.

10. An amplifier chain comprising:

a first amplifier stage;

a final amplifier stage positioned in series with said first amplifier stage;

a feedback loop comprising a switch and a impedance element, said feedback loop associated with said first amplifier stage;

said amplifier stages operating in a saturated mode when said switch is open; and

said amplifier stages operating in a linear mode when said switch is closed.

11. The amplifier chain of claim 10 further comprising a second amplifier stage positioned in series between said first amplifier stage and said final amplifier stage.

12. The amplifier chain of claim 11 wherein said final amplifier stage comprises a plurality of parallel transistor cells.

13. The amplifier chain of claim 10 wherein said final amplifier stage comprises a plurality of parallel transistor cells.

14. The amplifier chain of claim 10 further comprising a bias circuit providing a bias current for basing said final amplifier stage.

15. The amplifier chain of claim 14 wherein said bias current increases when said switch is closed.

16. The amplifier chain of claim 10 wherein said amplifier chain is adapted for use in a GMSK mode when said switch is open.

17. The amplifier chain of claim 10 wherein said amplifier chain is adapted for use in an 8-PSK mode when said switch is closed.

18. The amplifier chain of claim 10 wherein said switch comprises a pin diode.

19. The amplifier chain of claim 12 wherein said plurality of transistor cells comprises forty-eight transistor cells.

20. An amplifier chain comprising:

a first amplifier stage;

a final amplifier stage positioned in series with said first amplifier stage;

a switch associated with said first amplifier stage;

said final amplifier stage comprising a plurality of transistors cells arranged in a parallel array;

said amplifier chain operating in a first mode when said switch is open and in a second mode when said switch is closed; and

said plurality of transistor cells all operating in said first mode and a portion of said plurality of transistor cells operating in said second mode.

21. The amplifier chain of claim 20 further comprising a second amplifier stage positioned in series between said first and said final amplifier stages.

22. The amplifier chain of claim 21 further comprising an impedance element associated with said switch, said impedance element and said switch forming a feedback loop for said first amplifier stage when said switch is closed.

23. The amplifier chain of claim 21 further comprising a bias circuit providing a bias current for each of said amplifier stages.

24. The amplifier chain of claim 23 wherein said bias circuit provides different bias currents according to the mode in which the amplifier chain is operating.

25. The amplifier chain of claim 20 wherein said amplifier chain operates in a saturated state when in said first mode.

26. The amplifier chain of claim 20 wherein said amplifier chain operates in a linear state when in said second mode.

27. The amplifier chain of claim 20 wherein said amplifier chain operates in a saturated state when in said first mode and a linear mode when in said second mode.

28. The amplifier chain of claim 20 wherein said amplifier chain operates in a GMSK mode when in said first mode.

29. The amplifier chain of claim 20 wherein said amplifier chain operates in an 8-PSK mode when in said second mode.

30. The amplifier chain of claim 20 wherein said portion of said plurality of transistor cells operating in said second mode comprises thirty-six of forty-eight transistor cells operating in said second mode.

31. A method of controlling an amplifier chain with a plurality of amplifier stages, comprising:

providing a switch associated with a first amplifier stage in the amplifier chain;

operating the amplifier chain in a first mode when said switch is open, said first mode comprising operating the amplifier stages in a saturated mode;

operating the amplifier chain in a second mode when said switch is closed, said second mode comprising operating at least one of said amplifier stages in a linear mode;

dampening gain associated with said first amplifier stage when said switch is closed; and

increasing a bias control signal to at least one of said amplifier stages when said switch is closed.

32. The method of claim 31 wherein dampening gain associated with said first amplifier stage when said switch is closed comprises bypassing said first amplifier stage.

33. The method of claim 31 wherein dampening gain associated with said first amplifier stage when said switch is closed comprises providing a feedback loop for said first amplifier stage.

34. The method of claim 31 further comprising varying a number of amplification elements in a final amplifier stage when said switch is closed.

35. The method of claim 31 further comprising operating the amplifier chain in a GMSK mode when said switch is open.

36. The method of claim 35 further comprising operating the amplifier chain in an 8-PSK mode when said switch is closed.