Byte alignment for serial data receiver

• US 6,724,328 B1
• Filed: 06/03/2003
• Issued: 04/20/2004
• Est. Priority Date: 06/03/2003
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Lam, John, Venkata, Ramanand, Lee, Chong H., Chan, Vinson, Lui, Henry Y., Kabani, Malik, Patel, Rakesh
• Primary Examiner(s): Young, Brian
• Assistant Examiner(s): LAUTURE, JOSEPH J
• Application Number:
  US10/454,626
• Time in Patent Office: 322 Days
• Field of Search: 341/101, 341/100, 711/20, 710/71, 712/300, 370/516, 375/137, 326/39
• US Class Current: 341/101
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00
• CPC Class Codes: H04L 7/0054 Detection of the synchronisation error by features other than the received signal transition by means of signal transition H04L7/033

Abstract

A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.

Claims

1. A method of aligning a boundary between bytes of a deserialized serial data signal that has been input into a programmable logic device, said programmable logic device having a serial data interface with a plurality of channels, and having a programmable logic core, said method comprising:

receiving a respective serial data signal on each respective channel of said serial data interface;

for each said channel, deserializing said serial data signal, including inserting an initial candidate byte boundary between selected bits of said deserialized data signal;

transmitting said deserialized data signal with said initial candidate byte boundary from each said channel of said serial data interface to said programmable logic core;

processing said deserialized signal with said initial candidate byte boundary on each said channel in said programmable logic core to validate each said initial candidate byte boundary; and

sending a respective byte alignment error signal from said programmable logic core to a respective channel of said serial data interface when said candidate boundary on said respective channel is determined to be invalid.

2. The method of claim 1 further comprising:

assigning based on said error signal an alternate candidate byte boundary between different selected bits of said deserialized data signal on said respective channel of said serial data interface;

retransmitting said deserialized data signal with said alternate candidate byte boundary from said respective channel of said serial data interface to said programmable logic core; and

reprocessing said retransmitted deserialized data signal with said alternate candidate byte boundary in said programmable logic core to validate said alternate candidate byte boundary.

3. The method of claim 2 wherein:

said error signal indicates a number of bits of discrepancy in said byte boundary; and

said assigning an alternate candidate byte boundary comprises moving said byte boundary by said number of bits of discrepancy.

4. The method of claim 2 wherein:

said assigning an alternate candidate byte boundary comprises moving said byte boundary by one bit; and

said sending, said assigning, said retransmitting and said reprocessing occur iteratively until said reprocessing determines that said alternate candidate byte boundary is correct.

5. A method of aligning a boundary between bytes of a deserialized serial data signal that has been input into a programmable logic device, said programmable logic device having a serial data interface with a plurality of channels, and having a programmable logic core, said method comprising:

receiving a respective serial data signal on each respective channel of said serial data interface;

for each said channel, deserializing said serial data signal, including inserting an initial candidate byte boundary between selected bits of said deserialized data signal;

transmitting said deserialized data signal with said initial candidate byte boundary from each said channel of said serial data interface to said programmable logic core; and

receiving a respective byte alignment error signal from said programmable logic core on a respective channel of said serial data interface when said candidate boundary is determined in said programmable logic core to be invalid.

6. The method of claim 5 further comprising:

assigning based on said error signal an alternate candidate byte boundary between different selected bits of said respective deserialized data signal on said respective channel of said serial data interface;

retransmitting said deserialized data signal with said alternate candidate byte boundary from said respective channel of said serial data interface to said programmable logic core; and

again receiving a byte alignment error signal from said programmable logic core on said respective channel of said serial data interface when said candidate boundary is determined in said programmable logic core to be invalid.

7. The method of claim 6 wherein:

said error signal indicates a number of bits of discrepancy in said byte boundary; and

said assigning an alternate candidate byte boundary comprises moving said byte boundary by said number of bits of discrepancy.

8. The method of claim 6 wherein:

said assigning an alternate candidate byte boundary comprises moving said byte boundary by one bit; and

said receiving, said assigning and said retransmitting occur iteratively until said alternate candidate byte boundary is determined in said programmable logic core to be correct.

9. A programmable logic device comprising:

a programmable logic core; and

a serial data interface adapted to receive and deserialize a serial data signal including a plurality of channels of serial data, said serial data interface comprising bit-slipping circuitry on each said channel adapted to insert a byte boundary between bits of each respective deserialized data signal on each said channel, said bit-slipping circuitry being responsive to a bit-slipping control signal from said programmable logic core.

10. The programmable logic device of claim 9 wherein said bit-slipping circuitry comprises bit-handling circuitry and control circuitry that controls said bit-handling circuitry responsive to said bit-slipping control signal.

11. The programmable logic device of claim 10 wherein:

each byte includes a first number of bits; and

said bit-handling circuitry comprises;

at least one shift register for receiving said serial data, and having capacity to hold a second number of bits greater than said first number of bits, and further having a number of parallel outputs equal to said second number of bits, and

selection circuitry having a number of selection inputs equal to said number of parallel outputs of said at least one shift register, and having a number of selection outputs equal to said first number of bits, said selection inputs being connected to said parallel outputs of said at least one shift register;

wherein;

said control circuitry controls which of said selection inputs is connected to said selection outputs.

12. The programmable logic device of claim 11 wherein said selection circuitry is a barrel shifter.

13. The programmable logic device of claim 11 wherein said second number of bits is twice said first number of bits.

14. The programmable logic device of claim 13 wherein said at least one shift register comprises two shift registers chained serially, each of said shift registers having capacity to hold said first number of bits.

15. A digital processing system comprising:

processing circuitry;

a memory coupled to said processing circuitry; and

a programmable logic device as defined in claim 9 coupled to the processing circuitry and the memory.

16. A printed circuit board on which is mounted a programmable logic device as defined in claim 9.

17. The printed circuit board defined in claim 16 further comprising:

memory circuitry mounted on the printed circuit board and coupled to the programmable logic device.

18. The printed circuit board defined in claim 17 further comprising:

processing circuitry mounted on the printed circuit board and coupled to the memory circuitry.

19. A serial data interface for use with a programmable logic device having a programmable logic core, said serial data interface being adapted to receive and deserialize a serial data signal including a plurality of channels of serial data, said serial data interface comprising:

bit-slipping circuitry on each of said channels adapted to insert a byte boundary between bits of each respective deserialized serial data signal on each respective channel, said bit-slipping circuitry being responsive to a bit-slipping control signal from said programmable logic core.

20. The serial data interface of claim 19 wherein said bit-slipping circuitry comprises bit-handling circuitry and control circuitry that controls said bit-handling circuitry responsive to said bit-slipping control signal.

21. The serial data interface of claim 20 wherein:

each byte includes a first number of bits; and

said bit-handling circuitry comprises;

at least one shift register for receiving said serial data, and having capacity to hold a second number of bits greater than said first number of bits, and further having a number of parallel outputs equal to said second number of bits, and

selection circuitry having a number of selection inputs equal to said number of parallel outputs of said at least one shift register, and having a number of selection outputs equal to said first number of bits, said selection inputs being connected to said parallel outputs of said at least one shift register;

wherein;

said control circuitry controls which of said selection inputs is connected to said selection outputs.

22. The serial data interface of claim 21 wherein said selection circuitry is a barrel shifter.

23. The serial data interface of claim 21 wherein said second number of bits is twice said first number of bits.

24. The serial data interface of claim 23 wherein said at least one shift register comprises two shift registers chained serially, each of said shift registers having capacity to hold said first number of bits.

25. A programmable logic device comprising the serial data interface of claim 19.

26. A digital processing system comprising:

processing circuitry;

a memory coupled to said processing circuitry; and

a programmable logic device as defined in claim 25 coupled to the processing circuitry and the memory.

27. A printed circuit board on which is mounted a programmable logic device as defined in claim 25.

28. The printed circuit board defined in claim 27 further comprising:

memory circuitry mounted on the printed circuit board and coupled to the programmable logic device.

29. The printed circuit board defined in claim 28 further comprising:

processing circuitry mounted on the printed circuit board and coupled to the memory circuitry.