Semiconductor device with improved latch arrangement

• US 6,724,657 B2
• Filed: 11/08/2002
• Issued: 04/20/2004
• Est. Priority Date: 06/14/2000
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Shukuri, Shoji
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US10/290,492
• Publication Number:
  US 20030067822A1
• Time in Patent Office: 529 Days
• Field of Search: 365/185.07, 365/185.08, 365/154
• US Class Current: 365/185.07
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 29/70 Masking faults in memories by using spares or by reconfiguring
• CPC Class Codes: G11C 29/789 using non-volatile cells or latches

Abstract

The nonvolatile memory includes a nonvolatile memory circuit that possesses a pair of series circuits of load elements and nonvolatile memory transistors, which are connected in a static latch configuration, a program control circuit that writes information into the nonvolatile memory circuit, a volatile latch circuit that latches information read from the nonvolatile memory circuit, and a readout control circuit that makes the volatile latch circuit latch the information read from the nonvolatile memory circuit. In response to the instruction of the readout operation, the readout control circuit supplies the operating voltage for the static latch operation to the nonvolatile memory circuit, and stops the supply of the operating voltage, after completing the latch operation.

Claims

1. A semiconductor device having a nonvolatile memory on a semiconductor substrate, wherein the nonvolatile memory comprises:

a plurality of nonvolatile memory circuits that include a pair of series circuits each of which includes a load element and a nonvolatile memory transistor connected in series, said pair of series circuits being connected in a static latch configuration, said nonvolatile memory transistor being a single layer polysilicon gate transistor;

a write-in control circuit that writes information into a plurality of the nonvolatile memory circuits;

a volatile latch circuit that latches information read from the nonvolatile memory circuits; and

a readout control circuit that makes the volatile latch circuit latch the information read from the nonvolatile memory circuits.

2. A semiconductor device according to claim 1, wherein the readout control circuit supplies an operating supply voltage for a static latch operation to a plurality of the nonvolatile memory circuits in response to an instruction of a reading operation, and stops supplying the operating supply voltage, after the volatile latch circuit completes the latch operation in response to the static latch operation.

3. A semiconductor device according to claim 2, wherein the instruction of the reading operation is given in response to a reset instruction to the semiconductor device.

4. A semiconductor device according to claim 1, further comprising an ECC circuit that inputs information latched by the volatile latch circuit to correct errors.

5. A semiconductor device according to claim 1, wherein:

the load elements included in each of the plural nonvolatile memory circuits are a first conductive type load transistor having a source, a drain, and a gate, and the nonvolatile memory transistors are a second conductive type transistor having a source, a drain, a floating gate, and a control gate;

the series circuit including the load transistor and the nonvolatile memory transistor includes an output node to couple the load transistor with the nonvolatile memory transistor, and a control node to couple the gate of the load transistor with the control gate of the nonvolatile memory transistor;

the output node of one series circuit of a pair of the series circuits is connected to the control node of the other series circuit to form the static latch configuration; and

complementary data lines are connected to a pair or the output nodes of a pair of the series circuits.

6. A semiconductor device according to claim 1, wherein:

the load elements included in each of the plural nonvolatile memory circuits are a first conductive type load transistor having a source, a drain, and a gate, and the nonvolatile memory transistors are a second conductive type transistor having a source, a drain, a floating gate, and a control gate;

the series circuit including the load transistor and the nonvolatile memory transistor includes an output node to couple the load transistor with the nonvolatile memory transistor, a program node to connect another nonvolatile memory transistor in series to the nonvolatile memory transistor coupled with the output node, and a control node to commonly couple the gate of the load transistor and the control gate of the nonvolatile memory transistor;

a pair of the series circuits has a static latch configuration in which the output node of one series circuit is mutually connected to the control node of the other series circuit; and

complementary data lines are connected to the output nodes of both the series circuits, and complementary program control lines are connected to the program nodes of both the series circuits.

7. A semiconductor device according to claim 1, wherein the nonvolatile memory transistor includes a MIS transistor having a second conductive type source and drain formed in a first conductive type semiconductor region, a gate insulating film formed on a channel between the source and the drain, and a floating gate formed art the gate insulating film, and a control gate being the second conductive type semiconductor region, underlying a gate insulating film formed beneath an extended portion of the floating gate.

8. A semiconductor device according to claim 1, wherein MIS transistors contained in a plurality of nonvolatile memory circuits and the write-in control circuit are the MIS transistor for use in a high voltage operation, and the MIS transistors contained in the volatile latch circuit and the readout control circuit are the MIS transistor for use in a low voltage operation.

9. A semiconductor device according to claim 7 or claim 8, further comprising a logic circuit and an external interface circuit each having the MIS transistors on the semiconductor substrate, wherein the gate insulating film of the nonvolatile memory transistors and the gate insulating film of the MIS transistors contained in the external interface circuit have a substantially equal thickness.

10. A semiconductor device according to claim 1 or claim 7, further comprising a logic circuit and an external interface circuit each having the MIS transistors on the semiconductor substrate, wherein the gate insulating film of the nonvolatile memory transistors is formed thicker than the gate insulating film of the MIS transistors contained in the logic circuit.

11. A semiconductor device according to claim 1, comprising on the substrate a to-be-relieved circuit and a relief circuit that replaces the to-be-relieved circuit, wherein the nonvolatile memory circuit stores relief information that specifies the to-be-relieved circuit to be replaced by the relief circuit.

12. A semiconductor device according to claim 11, further comprising a fuse programming circuit that stores the relief information in accordance with a fusing state of a fuse element, as another circuit to store the relief information for the to-be-relieved circuit.

13. A semiconductor device according to claim 11 or claim 12, wherein the to-be-relieved circuit is a memory coil array of a DRAM chip.

14. A semiconductor device according to claim 11 or claim 12, wherein the to-be-relieved circuit is a memory cell array of a microcomputer built-in DRAM.

15. A semiconductor device according to claim 11 or claim 12, wherein the to-be-relieved circuit is a memory cell array of a microcomputer built-in SRAM.

16. A semiconductor device according to claim 11 or claim 12, wherein a part of the plural nonvolatile memory circuits is served as a region to hold error correction codes of the relief information that the remaining nonvolatile memory circuits hold, and includes an ECC circuit capable of error corrections relating to readout information of the plural nonvolatile memory circuits.

17. A semiconductor device according to claim 16, whe rein the write-in control circuit has an operation mode that inhibits a write-in operation to the nonvolatile memory circuits.

18. A semiconductor device having a nonvolatile memory on a semiconductor substrate, wherein the nonvolatile memory comprises a plurality of nonvolatile memory circuits including a pair of series circuits each including a load element and plural nonvolatile memory transistors in series therewith, and said pair of series circuits being connected in a static latch configuration, wherein said plurality of nonvolatile memory transistors comprise single layer polysilicon gate transistors.

19. A semiconductor device according to claim 18, wherein:

the load elements included in each of the plural nonvolatile memory circuits are a first conductive type load transistor having a source, a drain, and a gate, and the nonvolatile memory transistors are a second conductive type transistor having a source, a drain, a floating gate, and a control gate;

the series circuit including the load transistor and the nonvolatile memory transistor includes an output node to couple the load transistor with the nonvolatile memory transistor, a program node to connect another nonvolatile memory transistor in series to the nonvolatile memory transistor coupled with the output node, and a control node to commonly couple the gate of the load transistor and the control gate of the nonvolatile memory transistor;

a pair of the series circuits has a static latch configuration in which the output node of one series circuit is mutually connected to the control node of the other series circuit; and

complementary data lines are connected to the output nodes of both the sense circuits, and complementary write-in control lines are connected to the control nodes of both the series circuits.

20. A semiconductor device according to claim 18, wherein the nonvolatile memory transistor Includes a MIS transistor having a second conductive type source and drain formed in a first conductive type semiconductor region, a gate insulating film formed on a channel between the source and the drain, and a floating gate formed on the gate insulating film, and a control gate being the second conductive type semiconductor region, underlying a gate insulating film formed beneath an extended portion of the floating gate.

21. A semiconductor device according to claim 18, comprising on the substrate a to-be-relieved circuit and a relief circuit that replaces the to-be-relieved circuit, wherein the nonvolatile memory circuit stores relief information that specifies the to-be-relieved circuit to be replaced by the relief circuit.

22. A semiconductor device comprising:

a memory circuit including a first load element and a first nonvolatile transistor that are connected in series, and a second load element and a second nonvolatile transistor that are connected in series, wherein said first and second nonvolatile transistors comprise single lay r polysilicon gate transistors; and

a hold circuit that holds information read from the memory circuit,

wherein the first nonvolatile transistor has a control terminal connected to a node that couples the second load element and the second nonvolatile transistor,

wherein the second nonvolatile transistor has a control terminal connected to a node that couples the first load element and the first nonvolatile transistor,

wherein the hold circuit is connected to the node coupling the first load element and the first nonvolatile transistor and the node coupling the second load element and the second nonvolatile transistor, and

wherein each of the first and second nonvolatile transistors includes a MIS transistor having a second conductive type source and drain formed in a first conductive type semiconductor region, a gate insulating film formed on a channel between the source and the drain, and a floating gate formed on the gate insulating film, and a control gate being the second conductive type semiconductor region, underlying a gate insulating film formed beneath an extended portion of the floating gate.

23. A semiconductor device comprising:

a memory circuit including a first load element and a first nonvolatile transistor that are connected in series, and a second load element and a second nonvolatile transistor that are connected in series, wherein said first and second nonvolatile transistors comprise single layer polysilicon gate transistors; and

a hold circuit that holds information read from the memory circuit,

wherein the first nonvolatile transistor has a control gate connected to a node that couples the second load element and the second nonvolatile transistor,

wherein the second nonvolatile transistor has a control gate connected to a node that couples the first load element and the first nonvolatile transistor,

wherein the hold circuit is connected to the node coupling the first load element and the first nonvolatile transistor and the node coupling the second load element and the second nonvolatile transistor, and

wherein each of the first and second nonvolatile transistors includes a source and drain formed in a semiconductor region of a semiconductor substrate, an insulating film formed on a channel region in the semiconductor region, a floating gate formed on the insulating film, and a control gate formed in the semiconductor region.

24. A semiconductor device according to claim 23, further comprising a plurality of memory cells, wherein the memory circuit is used to store relief addresses of the plural memory cells.

25. A semiconductor device according to claim 23, wherein the first and the second nonvolatile transistors are EEPROM memory cells.

26. A semiconductor device according to claim 23, wherein the hold circuit is a latch circuit.

27. A semiconductor device according to claim 23, wherein the first and the second load elements are MIS transistors.