Memory device and method for selectable sub-array activation
First Claim
Patent Images
1. A memory device comprising:
- a memory array comprising a plurality of groups of sub-arrays;
a register; and
circuitry operative to simultaneously write data into N number of groups of sub-arrays, wherein N is a value stored in the register.
10 Assignments
0 Petitions
Accused Products
Abstract
A memory device and method for selectable sub-array activation. In one preferred embodiment, a memory array is provided comprising a plurality of groups of sub-arrays and circuitry operative to simultaneously write data into and/or read data from a selected number of groups of sub-arrays. By selecting the number of groups of sub-arrays into which data is written and/or from which data is read, the write and/or read data rate is varied. Such varying can be used to prevent thermal run-away of the memory array. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
49 Citations
11 Claims
-
1. A memory device comprising:
-
a memory array comprising a plurality of groups of sub-arrays;
a register; and
circuitry operative to simultaneously write data into N number of groups of sub-arrays, wherein N is a value stored in the register. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
a plurality of data registers coupled with the plurality of groups of sub-arrays;
register selection logic coupled with the plurality of data registers and the register; and
sub-array group selection logic coupled with the plurality of groups of sub-arrays and the register.
-
-
6. The invention of claim 1 further comprising:
-
a data register comprising a plurality of register ports coupled with the plurality of groups of sub-arrays;
port control logic coupled with the plurality of registers ports and the register; and
sub-array group selection logic coupled with the plurality of groups of sub-arrays and the register.
-
-
7. The invention of claim 1 further comprising:
-
a data register;
a variable serial-to-parallel connection circuit, the variable serial-to-parallel connection circuit coupled with the register and coupling the data register to the plurality of groups of sub-arrays; and
sub-array group selection logic coupled with the plurality of groups of sub-arrays and the register.
-
-
8. The invention of claim 1, wherein the memory array comprises a three-dimensional memory array.
-
9. The invention of claim 1, wherein the memory array comprises a plurality of antifuse memory cells.
-
10. The invention of claim 1, wherein the memory array comprises a plurality of write-once memory cells.
-
11. The invention of claim 1, wherein the memory array comprises a plurality of write-many memory cells.
Specification
-
- Resources
Litigation Campaign Assessment
Thank you for your request. You will receive a custom alert email when the Litigation Campaign Assessment is available.
×
-
Current AssigneeSanDisk Technologies LLC (Western Digital Corporation)
-
Original AssigneeMatrix Semiconductor, Inc. (Western Digital Corporation)
-
InventorsKleveland, Bendik, Scheuerlein, Roy E.
-
Primary Examiner(s)Lebentritt, Michael S.
-
Assistant Examiner(s)Nguyen, Tuan T.
-
Application NumberUS09/943,655Publication NumberTime in Patent Office963 DaysField of Search365/189.11, 365/230.03US Class Current365/189.12CPC Class CodesG11C 2207/107 Serial-parallel conversion ...G11C 7/04 with means for avoiding dis...G11C 7/1051 Data output circuits, e.g. ...G11C 7/106 Data output latchesG11C 7/1078 Data input circuits, e.g. w...G11C 7/1087 Data input latchesG11C 7/20 Memory cell initialisation ...G11C 8/12 Group selection circuits, e...
